{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,20]],"date-time":"2026-06-20T16:43:47Z","timestamp":1781973827337,"version":"3.54.5"},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/OAPA.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2019]]},"DOI":"10.1109\/access.2019.2895057","type":"journal-article","created":{"date-parts":[[2019,1,25]],"date-time":"2019-01-25T20:21:38Z","timestamp":1548447698000},"page":"17256-17262","source":"Crossref","is-referenced-by-count":29,"title":["Low Leakage Current Symmetrical Dual-k 7 nm Trigate Bulk Underlap FinFET for Ultra Low Power Applications"],"prefix":"10.1109","volume":"7","author":[{"given":"Mahmoud S.","family":"Badran","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1821-9628","authenticated-orcid":false,"given":"Hanady Hussein","family":"Issa","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9304-6048","authenticated-orcid":false,"given":"Saleh M.","family":"Eisa","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hani Fikry","family":"Ragai","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2626397"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1016\/S0026-2714(02)00027-6"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2013.2250975"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.3390\/mi8110330"},{"key":"ref12","year":"2016","journal-title":"Sentaurus User&#x2019;s Manual"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2523885"},{"key":"ref14","first-page":"157","article-title":"Parasitic resistances and capacitances","author":"chauhan","year":"2015","journal-title":"FinFET Modeling for IC Simulation and Design"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2007.911974"},{"key":"ref16","first-page":"629","article-title":"Hard and soft-breakdown characteristics of ultra-thin HfO2 under dynamic and constant voltage stress","author":"kim","year":"2002","journal-title":"IEDM Tech Dig"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2009.12.002"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4418914"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2004.1419167"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/HKEDM.1997.642325"},{"key":"ref4","first-page":"251","article-title":"FinFET scaling to 10 nm gate length","author":"yu","year":"2002","journal-title":"IEDM Tech Dig"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1016\/S0038-1101(01)00035-1"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MCD.2004.1263404"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2391632"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1016\/S0038-1101(00)00187-8"},{"key":"ref5","year":"2015","journal-title":"International Technology Roadmap for Semiconductors (ITRS)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.896387"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2004.841333"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/5.371968"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/N-SSC.2006.4785860"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2014.2304711"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2004.828570"},{"key":"ref22","year":"2013","journal-title":"Three-dimensional Simulation of 20 Nm FinFETs with Round Fin Corners and Tapered Fin Shape of TCAD Sentaurus"},{"key":"ref21","year":"2016","journal-title":"Sentaurus Device User Guide Ver"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1016\/0038-1101(92)90325-7"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1016\/S1386-9477(03)00290-X"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2001.979588"},{"key":"ref25","doi-asserted-by":"crossref","first-page":"2363","DOI":"10.1109\/16.337450","article-title":"on the universality of inversion layer mobility in si mosfet's: part ii-effects of surface orientation","volume":"41","author":"takagi","year":"1994","journal-title":"IEEE Transactions on Electron Devices"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/8600701\/08626090.pdf?arnumber=8626090","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,27]],"date-time":"2022-01-27T07:27:44Z","timestamp":1643268464000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8626090\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"references-count":31,"URL":"https:\/\/doi.org\/10.1109\/access.2019.2895057","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019]]}}}