{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T20:18:21Z","timestamp":1740169101036,"version":"3.37.3"},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/OAPA.html"}],"funder":[{"DOI":"10.13039\/501100003977","name":"Israel Science Foundation","doi-asserted-by":"publisher","award":["996\/18","2181\/18"],"award-info":[{"award-number":["996\/18","2181\/18"]}],"id":[{"id":"10.13039\/501100003977","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2019]]},"DOI":"10.1109\/access.2019.2901738","type":"journal-article","created":{"date-parts":[[2019,2,27]],"date-time":"2019-02-27T20:24:01Z","timestamp":1551299041000},"page":"27641-27649","source":"Crossref","is-referenced-by-count":6,"title":["Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection"],"prefix":"10.1109","volume":"7","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1410-4746","authenticated-orcid":false,"given":"Robert","family":"Giterman","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Roman","family":"Golman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Adam","family":"Teman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"CoreMark Benchmark","year":"2013","key":"ref31"},{"key":"ref30","first-page":"1","article-title":"PSP-cache: A low-cost fault-tolerant cache memory architecture","author":"farbeh","year":"2014","journal-title":"Proc IEEE Design Autom Test Eur Conf (DATE)"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2512706"},{"key":"ref11","first-page":"308","article-title":"An 800 MHz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications","author":"giterman","year":"2017","journal-title":"Proc IEEE Eur Solid-State Circuits Conf (ESSCIRC)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2305016"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0783"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.52"},{"key":"ref15","first-page":"88","article-title":"Delay and area efficient first-level cache soft error detection and correction","author":"mohr","year":"2007","journal-title":"Proc Int Conf Comput Design (ICCD)"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.19"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1016\/j.future.2015.03.001"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2820145"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2603923"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2008.4681832"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2518220"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815973"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FTFC.2014.6828617"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2305016"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-DAT.2015.7114576"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-60402-2"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea3020054"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2394459"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2574353"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865600"},{"journal-title":"ITRS","year":"2015","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7527413"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744871"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2747087"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1950.tb00463.x"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2015.7182027"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763257"},{"key":"ref25","doi-asserted-by":"crossref","first-page":"395","DOI":"10.1147\/rd.144.0395","article-title":"A class of optimal minimum odd-weight-column SEC-DED codes","volume":"14","author":"hsiao","year":"1970","journal-title":"IBM J Res Develop"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/8600701\/08653811.pdf?arnumber=8653811","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,8,10]],"date-time":"2021-08-10T19:41:00Z","timestamp":1628624460000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8653811\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"references-count":31,"URL":"https:\/\/doi.org\/10.1109\/access.2019.2901738","relation":{},"ISSN":["2169-3536"],"issn-type":[{"type":"electronic","value":"2169-3536"}],"subject":[],"published":{"date-parts":[[2019]]}}}