{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T16:33:20Z","timestamp":1782923600360,"version":"3.54.5"},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/OAPA.html"}],"funder":[{"name":"China NSF for Young Scientists","award":["61501250"],"award-info":[{"award-number":["61501250"]}]},{"DOI":"10.13039\/501100001809","name":"NSFC","doi-asserted-by":"crossref","award":["61871376"],"award-info":[{"award-number":["61871376"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100001809","name":"NSFC","doi-asserted-by":"crossref","award":["61871234"],"award-info":[{"award-number":["61871234"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"name":"SRF for ROCS, SEM"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2019]]},"DOI":"10.1109\/access.2019.2904746","type":"journal-article","created":{"date-parts":[[2019,3,13]],"date-time":"2019-03-13T19:05:55Z","timestamp":1552503955000},"page":"37131-37140","source":"Crossref","is-referenced-by-count":8,"title":["Protograph QC-LDPC and Rate-Adaptive Polar Codes Design for MLC NAND Flash Memories"],"prefix":"10.1109","volume":"7","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0278-2451","authenticated-orcid":false,"given":"Lingjun","family":"Kong","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6111-092X","authenticated-orcid":false,"given":"Yahui","family":"Liu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Haiyang","family":"Liu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shengmei","family":"Zhao","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","first-page":"6","article-title":"Optimized degree distributions for binary and non-binary LDPC codes in Flash memory","author":"vakilinia","year":"2014","journal-title":"Proc Int Symp Inf Theory Appl (ISITA)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSAC.2016.2603719"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2013.2248351"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.2009.2021379"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.2005.862081"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/WCNCW.2017.7919040"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICC.2013.6655078"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/LCOMM.2014.2364845"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICCNC.2015.7069414"},{"key":"ref19","author":"song","year":"2018","journal-title":"Polar-coded forward error correction for MLC NAND flash memory polar FEC for NAND flash memory"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2160747"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2602359"},{"key":"ref3","first-page":"521","article-title":"Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis","author":"cai","year":"2012","journal-title":"Proc Conf Design Autom Test Eur (DATE)"},{"key":"ref6","first-page":"329","article-title":"A 2.4 pJ\/bit, 6.37 Gb\/s SPC-enhanced BC-BCH decoder in 65 nm CMOS for NAND flash storage systems","author":"jung","year":"2018","journal-title":"Asia South Pacific Design Autom Conf (ASP-DAC)"},{"key":"ref5","first-page":"94","article-title":"Error correction for multi-level NAND flash memory using Reed-Solomon codes","author":"chen","year":"2008","journal-title":"Proc IEEE Workshop Signal Process Syst (WSPS)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/LCOMM.2018.2814985"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2071990"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSAC.2016.2603660"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSAC.2014.140508"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669118"},{"key":"ref20","first-page":"1","article-title":"On the use of strong BCH codes for improving multilevel NAND flash memory storage capacity","author":"sun","year":"2006","journal-title":"Proc IEEE Workshop Signal Process Syst (SiPS) Design Implement"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISIT.2011.6033837"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2004.826370"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.2013.2272694"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.2006.887082"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TENCONSpring.2013.6584444"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISWCS.2011.6125398"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/8600701\/08666631.pdf?arnumber=8666631","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,8,10]],"date-time":"2021-08-10T19:40:46Z","timestamp":1628624446000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8666631\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/access.2019.2904746","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019]]}}}