{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,8]],"date-time":"2025-11-08T12:16:11Z","timestamp":1762604171163,"version":"3.37.3"},"reference-count":50,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/OAPA.html"}],"funder":[{"DOI":"10.13039\/501100001659","name":"Deutsche Forschungsgemeinschaft","doi-asserted-by":"publisher","award":["318642660"],"award-info":[{"award-number":["318642660"]}],"id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002347","name":"Bundesministerium f\u00fcr Bildung und Forschung","doi-asserted-by":"publisher","award":["03ZZ0512A"],"award-info":[{"award-number":["03ZZ0512A"]}],"id":[{"id":"10.13039\/501100002347","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2019]]},"DOI":"10.1109\/access.2019.2907156","type":"journal-article","created":{"date-parts":[[2019,4,15]],"date-time":"2019-04-15T21:58:06Z","timestamp":1555365486000},"page":"44489-44502","source":"Crossref","is-referenced-by-count":13,"title":["Data Link Layer Processor for 100 Gbps Terahertz Wireless Communications in 28 nm CMOS Technology"],"prefix":"10.1109","volume":"7","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2349-298X","authenticated-orcid":false,"given":"Lukasz","family":"Lopacinski","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Miroslav","family":"Marinkovic","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Goran","family":"Panic","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohamed Hussein","family":"Eissa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alireza","family":"Hasani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Karthik","family":"Krishnegowda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rolf","family":"Kraemer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"LogiCORETM IP Reed-Solomon Decoder Product Guide","year":"2015","key":"ref39"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/PIMRC.2012.6362670"},{"journal-title":"Decode Binary Low-Density Parity-Check Code Specified by Parity-Check Matrix–Simulink–MathWorks Switzerland","year":"2019","key":"ref33"},{"journal-title":"Low-Density Parity-Check Codes From DVB-S 2 Standard—MATLAB DVBS2LDPC","year":"2019","key":"ref32"},{"journal-title":"Frame structure channel coding and modulation for a second generation digital terrestrial television broadcasting system (DVB-T2)","first-page":"1","year":"2010","key":"ref31"},{"key":"ref30","first-page":"333","article-title":"100 Gbps wireless—Data link layer VHDL implementation","author":"lopacinski","year":"2015","journal-title":"Proc 18th Conf Reconfigurable Ubiquitous Comput (RUC)"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/PIMRC.2010.5671892"},{"journal-title":"LogiCORE IP Viterbi Decoder v9 0—Product Guide Xilinx Datasheet","year":"2014","key":"ref36"},{"journal-title":"Performance and Resource Utilization for LDCP Encoder\/Decoder","year":"2019","key":"ref35"},{"journal-title":"3GPP Turbo Decoder v4 0","year":"2009","key":"ref34"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1155\/2017\/3560521"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/URSI-AT-RASC.2015.7302987"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1016\/j.aeue.2017.07.005"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/WAMICON.2014.6857743"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IRMMW-THz.2014.6956202"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"2532","DOI":"10.1109\/JSSC.2018.2839037","article-title":"Wideband 240-GHz transmitter and receiver in BiCMOS technology with 25-Gbit\/s data rate","volume":"53","author":"eissa","year":"2018","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/GSMM.2018.8439259"},{"journal-title":"IHP ASIC Technologies","year":"2019","key":"ref21"},{"key":"ref24","first-page":"13","article-title":"Benchmarking of WSN Solutions and IEEE 802.15. 4-2006 PSSS based solutions","author":"wolf","year":"2010","journal-title":"Proc 9 GI\/ITG KuVS Fachgespräch Sensornetze"},{"key":"ref23","first-page":"1","article-title":"System design considerations for a PSSS transceiver for 100 Gbps wireless communication with emphasis on mixed signal implementation","author":"javed","year":"2015","journal-title":"Proc IEEE 11th Annu Wireless Microw Technol Conf (WAMICON)"},{"key":"ref26","first-page":"262","article-title":"PSSS—Parallel sequence spread spectrum a physical layer for RF communication","author":"schwetlick","year":"2004","journal-title":"Proc IEEE Int Symp Consum Electron"},{"key":"ref25","article-title":"PSSS-parallel sequence spread spectrum a potential physical layer for OBAN?","author":"schwetlick","year":"2005","journal-title":"Proc OBAN Workshop Mobility QoS Secur Open Wireless Access Netw 14th IST Mobile Wireless Commun Summit"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/ISIT.2006.261711"},{"journal-title":"Improving goodput and reliability of ultra-high-speed wireless communication at data link layer level","year":"2017","author":"lopacinski","key":"ref10"},{"key":"ref11","first-page":"86","article-title":"100 Gbps wireless—Challenges to the data link layer","author":"lopacinski","year":"2014","journal-title":"Proc Inf Commun Technol Forum IEICE ICTF"},{"journal-title":"7 Series FPGAs GTX\/GTH Transceivers Xilinx Datasheet","year":"2012","key":"ref40"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/SiPS.2013.6674497"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-10569-7_2"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISTC.2016.7593146"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/SiPS.2017.8109974"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2014.73"},{"journal-title":"International Technology Roadmap for Semiconductors 2 0 Executive Report","year":"2015","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1587\/transele.E98.C.1081"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICIPRM.2013.6562647"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2015.2504930"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/COMCAS.2015.7360436"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884820"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TAP.2009.2029290"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1515\/freq-2017-0174"},{"key":"ref7","first-page":"827","article-title":"On-chip integrated distributed amplifier and antenna systems in SiGe BiCMOS for transceivers with ultra-large bandwidth","volume":"71","author":"testa","year":"2017","journal-title":"Frequenz"},{"key":"ref49","first-page":"1289","article-title":"A 6.16 Gb\/s 4.7 pJ\/bit\/iteration LDPC decoder for IEEE 802.11ad standard in 40 nm LP-CMOS","author":"motozuka","year":"2015","journal-title":"Proc IEEE Global Conf Signal Inf Process (GlobalSIP)"},{"key":"ref9","first-page":"96","article-title":"A 100 Gbps data link layer with an adaptive algorithm for forward error correction","author":"lopacinski","year":"2015","journal-title":"Proc Inf Commun Technol Forum IEICE ICTF"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2017.2745704"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/JLT.2016.2598440"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/SiPS.2013.6674490"},{"key":"ref47","first-page":"1","article-title":"An energy efficient 18 Gbps LDPC decoding processor for 802.11ad in 28 nm CMOS","author":"li","year":"2015","journal-title":"Proc IEEE Asian Solid-State Circuits Conf (A-SSCC)"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/VTCSpring.2018.8417522"},{"key":"ref41","first-page":"1","article-title":"Design and performance measurements of an FPGA accelerator for a 100 Gbps wireless data link layer","author":"lopacinski","year":"2015","journal-title":"1st URSI Atlantic Radio Science Conference (URSI AT-RASC)"},{"key":"ref44","first-page":"464","article-title":"A scalable 1.5-to-6Gb\/s 6.2-to-38.1 mW LDPC decoder for 60 GHz wireless networks in 28 nm UTBB FDSOI","author":"weiner","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2015.32"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/8600701\/08685101.pdf?arnumber=8685101","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,8,10]],"date-time":"2021-08-10T19:40:39Z","timestamp":1628624439000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8685101\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"references-count":50,"URL":"https:\/\/doi.org\/10.1109\/access.2019.2907156","relation":{},"ISSN":["2169-3536"],"issn-type":[{"type":"electronic","value":"2169-3536"}],"subject":[],"published":{"date-parts":[[2019]]}}}