{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,3]],"date-time":"2025-12-03T03:33:34Z","timestamp":1764732814124,"version":"3.37.3"},"reference-count":44,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Basic Research Program of China","doi-asserted-by":"publisher","award":["2017YFB1001603"],"award-info":[{"award-number":["2017YFB1001603"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61672251","61732010","61825202"],"award-info":[{"award-number":["61672251","61732010","61825202"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2019]]},"DOI":"10.1109\/access.2019.2931058","type":"journal-article","created":{"date-parts":[[2019,7,25]],"date-time":"2019-07-25T15:47:14Z","timestamp":1564069634000},"page":"103517-103529","source":"Crossref","is-referenced-by-count":12,"title":["NGraph: Parallel Graph Processing in Hybrid Memory Systems"],"prefix":"10.1109","volume":"7","author":[{"given":"Wei","family":"Liu","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4290-1408","authenticated-orcid":false,"given":"Haikun","family":"Liu","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6302-813X","authenticated-orcid":false,"given":"Xiaofei","family":"Liao","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3934-7605","authenticated-orcid":false,"given":"Hai","family":"Jin","sequence":"additional","affiliation":[]},{"given":"Yu","family":"Zhang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Graph500","year":"2010","key":"ref39"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1137\/1.9781611972740.43"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/1772690.1772751"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/2442516.2442530"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342227"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/2814576.2814806"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00051"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/3079079.3079097"},{"key":"ref35","first-page":"441","article-title":"Cgraph: A correlations-aware approach for efficient concurrent iterative graph processing","author":"zhang","year":"2018","journal-title":"Proc USENIX Annu Tech Conf"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/2600212.2600222"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2006.1705247"},{"journal-title":"SnAP","year":"2014","key":"ref40"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1088\/1674-4926\/38\/7\/071002"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2668128"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2819001.2819005"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2017.135"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342150"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2018.2876201"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/s11432-015-0764-7"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2004.840847"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1016\/S0079-6425(02)00012-9"},{"key":"ref28","first-page":"23","article-title":"PTLsim: A cycle accurate full system \n$ \\times $\n86&#x2013;64 microarchitectural simulator","author":"yourst","year":"2007","journal-title":"Proc IEEE Int Symp Perform Anal Syst Softw"},{"key":"ref4","article-title":"Graphx: Unifying data-parallel and graph-parallel analytics","author":"xin","year":"2014","journal-title":"arXiv 1402 2394"},{"key":"ref27","first-page":"29","article-title":"Marss-\n$ \\times $\n86: A qemu-based micro-architectural and systems simulator for \n$ \\times $\n86 multicore processors","author":"patel","year":"2011","journal-title":"Proceedings of the 1st International QEMU Users' Forum"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.14778\/2212351.2212354"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2517349.2522740"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2592798.2592814"},{"key":"ref5","first-page":"31","article-title":"Graphchi: Large-scale graph computation on just a PC","author":"kyrola","year":"2012","journal-title":"Proc USENIX Symp on Operating System Design and Implementation"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/s11432-017-9226-8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICDE.2015.7113362"},{"key":"ref2","first-page":"17","article-title":"Powergraph: Distributed graph-parallel computation on natural graphs","author":"gonzalez","year":"2012","journal-title":"Proc USENIX Symp on Operating System Design and Implementation"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2018.2847278"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1807167.1807184"},{"key":"ref20","first-page":"1","article-title":"45 nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T\/1MTJ cell","author":"lin","year":"2009","journal-title":"IEDM Tech Dig"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1785414.1785441"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908001"},{"key":"ref42","first-page":"375","article-title":"Gridgraph: Large-scale graph processing on a single machine using 2-level hierarchical partitioning","author":"zhu","year":"2015","journal-title":"Proc USENIX Annu Tech Conf"},{"key":"ref24","article-title":"Basic performance measurements of the intel optane DC persistent memory module","author":"izraelevitz","year":"2019","journal-title":"arXiv 1903 05714"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/2901318.2901344"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3079079.3079089"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/2925426.2926254"},{"key":"ref26","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","article-title":"The gem5 simulator","volume":"39","author":"binkert","year":"2011","journal-title":"ACM SIGARCH Comput Archit News"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/2858788.2688507"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485963"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/8600701\/08772041.pdf?arnumber=8772041","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:32:58Z","timestamp":1641987178000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8772041\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"references-count":44,"URL":"https:\/\/doi.org\/10.1109\/access.2019.2931058","relation":{},"ISSN":["2169-3536"],"issn-type":[{"type":"electronic","value":"2169-3536"}],"subject":[],"published":{"date-parts":[[2019]]}}}