{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,19]],"date-time":"2026-03-19T14:32:37Z","timestamp":1773930757099,"version":"3.50.1"},"reference-count":48,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"name":"High Security Level Network Infrastructure Key Equipment Core Chip and Software Development","award":["2017ZX01030301"],"award-info":[{"award-number":["2017ZX01030301"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2019]]},"DOI":"10.1109\/access.2019.2934390","type":"journal-article","created":{"date-parts":[[2019,8,9]],"date-time":"2019-08-09T15:54:04Z","timestamp":1565366044000},"page":"112448-112458","source":"Crossref","is-referenced-by-count":8,"title":["A Memory-Reinforced Tabu Search Algorithm With Critical Path Awareness for HW\/SW Partitioning on Reconfigurable MPSoCs"],"prefix":"10.1109","volume":"7","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7271-4107","authenticated-orcid":false,"given":"Zhongfu","family":"Guo","sequence":"first","affiliation":[]},{"given":"Xingming","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Bo","family":"Zhao","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/785411.785412"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1016\/j.cor.2012.04.013"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1299\/jamdsm.2017jamdsm0060"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1007\/978-81-322-1958-3_2"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.4304\/jcp.9.6.1309-1315"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-99259-4_2"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-010-9068-9"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1016\/j.neucom.2013.08.035"},{"key":"ref35","first-page":"532","article-title":"Application of improved simulated annealing optimization algorithms in hardware\/software partitioning of the reconfigurable system-on-chip","author":"jing","year":"2013","journal-title":"Proc Int Conf Parallel Comput Fluid Dyn"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1023\/A:1016567828852"},{"key":"ref10","article-title":"Real-time hardware\/software co-design using devs-based transparent M&S framework","author":"risco-mart\u00edn","year":"2016","journal-title":"Proc Summer Comput Simul Conf"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2017.2701828"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2645204"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.173"},{"key":"ref13","first-page":"263","article-title":"A comprehensive survey on hardware\/software partitioning process in co-design","volume":"14","author":"mhadhbi","year":"2016","journal-title":"Int J Comput Sci Inf Secur"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2519895"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2017.2776295"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2017.03.006"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/EURMIC.1997.617393"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-019-09220-7"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-013-0283-4"},{"key":"ref28","author":"wolf","year":"1997","journal-title":"Hardware\/Software Co-Design Principles and Practice"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/SMARTCOMP.2016.7501699"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1016\/j.ipl.2005.12.008"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/972627.972637"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-015-0994-4"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ICIS.2009.152"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/s11766-019-3706-1"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/s11432-015-0594-2"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISPA\/IUCC.2017.00121"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.4018\/978-1-4666-5888-2.ch350"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1142\/S0218843017410015"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/40.782564"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-33078-0_24"},{"key":"ref20","article-title":"Power and execution time optimization through hardware software partitioning algorithm for core based embedded system","volume":"2017","author":"hassine","year":"2017","journal-title":"J Optim"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1088\/1742-6596\/1237\/4\/042010"},{"key":"ref48","first-page":"215","article-title":"MPSOC workflow scheduling method and scheduling trigger mechanism based on virtual microscope technology","volume":"28","author":"guo","year":"2019","journal-title":"Acta Microscopica"},{"key":"ref22","first-page":"19","article-title":"HW\/SW Partitioning Algorithms for Multi-objective Optimization in Embedded Systems","volume":"2","author":"iguider","year":"2019","journal-title":"Int J Infor Sci Techq"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4613-0303-9_33"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-008-9032-0"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1002\/0470121173"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/92.661251"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1007\/978-81-322-1958-3_1"},{"key":"ref23","article-title":"Hardware accelerator for duo-binary CTC decoding: Algorithm selection, HW\/SW partitioning and FPGA implementation","author":"bj\u00e4rmark","year":"2006"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/CSSE.2008.488"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1044111.1044119"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1016\/j.mcm.2012.11.001"},{"key":"ref25","first-page":"458","article-title":"Accelerating real-time computer vision applications using HW\/SW co-design","author":"b k","year":"2017","journal-title":"Proc Int Conf Comput Commun Electron"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/8600701\/08793077.pdf?arnumber=8793077","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:32:40Z","timestamp":1641987160000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8793077\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"references-count":48,"URL":"https:\/\/doi.org\/10.1109\/access.2019.2934390","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019]]}}}