{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,11]],"date-time":"2026-06-11T16:46:09Z","timestamp":1781196369143,"version":"3.54.1"},"reference-count":40,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"DOI":"10.13039\/501100003329","name":"Ministerio de Econom\u00eda y Competitividad","doi-asserted-by":"publisher","award":["TIN2013-41129-P"],"award-info":[{"award-number":["TIN2013-41129-P"]}],"id":[{"id":"10.13039\/501100003329","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003329","name":"Ministerio de Econom\u00eda y Competitividad","doi-asserted-by":"publisher","award":["TIN2016-76373-P"],"award-info":[{"award-number":["TIN2016-76373-P"]}],"id":[{"id":"10.13039\/501100003329","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100010801","name":"Xunta de Galicia","doi-asserted-by":"publisher","award":["GRC 2014\/008"],"award-info":[{"award-number":["GRC 2014\/008"]}],"id":[{"id":"10.13039\/501100010801","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100008425","name":"Conseller\u00eda de Cultura, Educaci\u00f3n e Ordenaci\u00f3n Universitaria, Xunta de Galicia","doi-asserted-by":"publisher","award":["ED431G\/08"],"award-info":[{"award-number":["ED431G\/08"]}],"id":[{"id":"10.13039\/501100008425","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100010801","name":"Xunta de Galicia","doi-asserted-by":"publisher","award":["2017\/077"],"award-info":[{"award-number":["2017\/077"]}],"id":[{"id":"10.13039\/501100010801","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100014440","name":"Ministerio de Ciencia, Innovaci\u00f3n y Universidades","doi-asserted-by":"publisher","award":["RYC-2017-23312"],"award-info":[{"award-number":["RYC-2017-23312"]}],"id":[{"id":"10.13039\/100014440","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2020]]},"DOI":"10.1109\/access.2020.2980925","type":"journal-article","created":{"date-parts":[[2020,3,17]],"date-time":"2020-03-17T02:29:46Z","timestamp":1584412186000},"page":"53196-53202","source":"Crossref","is-referenced-by-count":154,"title":["Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes"],"prefix":"10.1109","volume":"8","author":[{"given":"Daniel","family":"Nagy","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2197-6251","authenticated-orcid":false,"given":"Gabriel","family":"Espineira","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7727-1704","authenticated-orcid":false,"given":"Guillermo","family":"Indalecio","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0574-1513","authenticated-orcid":false,"given":"Antonio J.","family":"Garcia-Loureiro","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6333-9189","authenticated-orcid":false,"given":"Karol","family":"Kalna","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0973-461X","authenticated-orcid":false,"given":"Natalia","family":"Seoane","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1063\/1.2802586"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2019.03.055"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2014.2367095"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1088\/0268-1242\/19\/4\/069"},{"key":"ref31","author":"ferry","year":"2000","journal-title":"Semiconductor Transport"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1088\/0268-1242\/27\/3\/039501"},{"key":"ref37","year":"2020","journal-title":"FoMPy"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2018.2804383"},{"key":"ref35","first-page":"33","article-title":"3D Schr&#x00F6;dinger equation quantum corrected Monte Carlo and drift diffusion simulations of stacked nanosheet gate-all-around transistor","author":"kalna","year":"2019","journal-title":"Proc IWCN Book Abstract"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2016.10.018"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838515"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1063\/1.3592252"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.901882"},{"key":"ref12","first-page":"1","article-title":"15nm-diameter 3D stacked nanowires with independent gates operation: \n$\\Phi$\nFFET","author":"dupre","year":"2008","journal-title":"IEDM Tech Dig"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/S3S.2015.7333521"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2017.2695455"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.3390\/ma12152391"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2013.2296209"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2013.2253465"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2004.834912"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.872693"},{"key":"ref28","author":"tomizawa","year":"1993","journal-title":"Numerical Simulation of Submicron Semiconductor Devices"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2018.2859799"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.902713"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2018.2825498"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2017.2769058"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1088\/0022-3719\/10\/10\/003"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2018.2858225"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDER.2005.1546612"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2018.2868379"},{"key":"ref2","first-page":"501","article-title":"Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology","author":"yakimets","year":"2017","journal-title":"IEDM Tech Dig"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2013.6724548"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2017.8268427"},{"key":"ref20","year":"2016","journal-title":"International Technology Roadmap for Semiconductors"},{"key":"ref22","first-page":"526","article-title":"Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond","author":"bangsaruntip","year":"2013","journal-title":"IEDM Tech Dig"},{"key":"ref21","first-page":"19","article-title":"A \n$0.063~\\mu\\text{m}^{2}$\n FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch","author":"basker","year":"2010","journal-title":"Proc Symp VLSI Technol"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2107990"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIT.2017.7998183"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.809431"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2519822"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/8948470\/09036890.pdf?arnumber=9036890","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T01:09:09Z","timestamp":1641949749000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9036890\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"references-count":40,"URL":"https:\/\/doi.org\/10.1109\/access.2020.2980925","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020]]}}}