{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,1]],"date-time":"2026-02-01T06:32:59Z","timestamp":1769927579763,"version":"3.49.0"},"reference-count":43,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Basic Research Program of China","doi-asserted-by":"publisher","award":["2017YFB1001603"],"award-info":[{"award-number":["2017YFB1001603"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61672251"],"award-info":[{"award-number":["61672251"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61732010"],"award-info":[{"award-number":["61732010"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61825202"],"award-info":[{"award-number":["61825202"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61929103"],"award-info":[{"award-number":["61929103"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2020]]},"DOI":"10.1109\/access.2020.2983065","type":"journal-article","created":{"date-parts":[[2020,3,24]],"date-time":"2020-03-24T22:31:36Z","timestamp":1585089096000},"page":"66304-66314","source":"Crossref","is-referenced-by-count":7,"title":["TLB Coalescing for Multi-Grained Page Migration in Hybrid Memory Systems"],"prefix":"10.1109","volume":"8","author":[{"given":"Xiaoyuan","family":"Wang","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4290-1408","authenticated-orcid":false,"given":"Haikun","family":"Liu","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6302-813X","authenticated-orcid":false,"given":"Xiaofei","family":"Liao","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3934-7605","authenticated-orcid":false,"given":"Hai","family":"Jin","sequence":"additional","affiliation":[]},{"given":"Yu","family":"Zhang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/1810085.1810109"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/1375634.1375641"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/1060289.1060299"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2749471"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835964"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.32"},{"key":"ref37","first-page":"2","article-title":"Architecting phase change memory as a scalable dram alternative","author":"benjamin lee","year":"2009","journal-title":"Proc 36th Annu Int Symp Comput Archit (ISCA)"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"ref35","doi-asserted-by":"crossref","first-page":"31","DOI":"10.1145\/36206.36181","article-title":"Machine-independent virtual memory management for paged uniprocessor and multiprocessor architectures","author":"rashid","year":"1987","journal-title":"Proc 2nd Int Conf Archit Support Program Lang Operating Syst (ASPLOS)"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003578"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1346281.1346286"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485943"},{"key":"ref11","year":"2020","journal-title":"Huge Pages Part 2 (Interfaces)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.10"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024738"},{"key":"ref14","first-page":"936","article-title":"An Operating System Level Data Migration Scheme in Hybrid DRAM-NVM Memory Architecture","author":"reza salkhordeh","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485963"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2402435"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2806887"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TKDE.2015.2427795"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.21"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2312005.2312018"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3079079.3079089"},{"key":"ref27","article-title":"Benchmarking modern multiprocessors","author":"bienia","year":"2011"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1995896.1995911"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.37"},{"key":"ref29","year":"0"},{"key":"ref5","first-page":"337","article-title":"Hash, don’t cache (the page table)","author":"yaniv","year":"2016","journal-title":"Proc ACM Sigmetrics Int Conf Meas Model Comput Sci"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540741"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815970"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630086"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056035"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"ref20","first-page":"268","article-title":"A 90 nm 4 Mb embedded phase-change memory with 1.2 V 12 ns read access time and 1 MB\/s write throughput","author":"de sandre","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2235013"},{"key":"ref21","first-page":"258","article-title":"A 64Mb MRAM with clamped-reference and adequate-reference schemes","author":"tsuchida","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830773"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1147\/rd.524.0465"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037704"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2009.30"},{"key":"ref26","year":"2020","journal-title":"SPEC CPU2006"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080217"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/3310133"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/8948470\/09046005.pdf?arnumber=9046005","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,10,19]],"date-time":"2022-10-19T17:50:50Z","timestamp":1666201850000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9046005\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"references-count":43,"URL":"https:\/\/doi.org\/10.1109\/access.2020.2983065","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020]]}}}