{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:33:03Z","timestamp":1758893583300,"version":"3.37.3"},"reference-count":37,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"name":"Science and Technology Research Project of Henan Province","award":["192102210131"],"award-info":[{"award-number":["192102210131"]}]},{"DOI":"10.13039\/100009555","name":"Doctoral Research Project of Henan Normal University","doi-asserted-by":"publisher","award":["5101119170144"],"award-info":[{"award-number":["5101119170144"]}],"id":[{"id":"10.13039\/100009555","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2020]]},"DOI":"10.1109\/access.2020.2985501","type":"journal-article","created":{"date-parts":[[2020,4,3]],"date-time":"2020-04-03T20:10:10Z","timestamp":1585944610000},"page":"224817-224824","source":"Crossref","is-referenced-by-count":3,"title":["An Efficient and Fast VLIW Compression Scheme for Stream Processor"],"prefix":"10.1109","volume":"8","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0864-4858","authenticated-orcid":false,"given":"Gongli","family":"Li","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0929-4477","authenticated-orcid":false,"given":"Yingying","family":"Hou","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4316-8570","authenticated-orcid":false,"given":"Junzhe","family":"Zhu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","first-page":"84","article-title":"Entropy coding techniques and protocol to support parallel processing with low latency","volume":"32","author":"zhou","year":"2013","journal-title":"Microcomput Appl"},{"key":"ref32","first-page":"8","article-title":"A fast parallel Huffman decoder for FPGA implementation","volume":"49","author":"acasandrei","year":"2008","journal-title":"Acta Technica Napocensis"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1016\/j.ipl.2017.09.011"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2921249"},{"key":"ref37","first-page":"251","article-title":"A bitmask-based code compression technique for embedded systems","author":"seong","year":"2006","journal-title":"Proc IEEE\/ACM Int Conf Comput Aided Design"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ICCE.2014.6776016"},{"key":"ref35","first-page":"22","article-title":"Research and implementation of VLIW compressing technology based on instruction prefix","volume":"39","author":"ji","year":"2013","journal-title":"Appl Electron Tech"},{"key":"ref34","first-page":"1379","article-title":"Optimized design research of instruction memory for stream architecture","volume":"40","author":"guan","year":"2012","journal-title":"Acta Electronica Sinica"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TII.2019.2948068"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1016\/j.jnca.2019.102457"},{"key":"ref12","first-page":"2833","article-title":"Design of block cipher processor based on stream processor architecture","volume":"12","author":"li","year":"2017","journal-title":"J Comput Res Develop"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TII.2019.2957130"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MSP.2007.915001"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2018.2869627"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TIP.2016.2551366"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ECACE.2017.7912997"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TLA.2015.7273793"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/s11042-019-07765-0"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1093\/bioinformatics\/btz922"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3093742.3093929"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICESS.Symposia.2008.9"},{"key":"ref3","first-page":"1359","article-title":"A dataflow-like driven reconfigurable manycore stream processor","volume":"34","author":"xu","year":"2013","journal-title":"J Chin Comput Syst"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"1691","DOI":"10.1109\/TVLSI.2011.2161499","article-title":"Homogeneous stream processors with embedded special function units for high-utilization programmable shaders","volume":"20","author":"kim","year":"2012","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref29","first-page":"225","article-title":"Instruction decompressor design for a VLIW processor","volume":"45","author":"buzdar","year":"2015","journal-title":"J Microelectron Electron Compon Mater"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2016.7869073"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TMM.2018.2890196"},{"key":"ref7","first-page":"1382","article-title":"Design and implementation of reconfigurable stream processor in multimedia applications","author":"xiao","year":"2008","journal-title":"Proc Int Conf Commun Circuits Syst"},{"journal-title":"Research and Design of Stream Processor","year":"2009","author":"zhang","key":"ref2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2911451.2926730"},{"journal-title":"Stream Processor Architecture","year":"2002","author":"rixner","key":"ref1"},{"key":"ref20","first-page":"2486","article-title":"Optimization algorithm and VLSI design of the arithmetic coder in JPEG2000","volume":"39","author":"liu","year":"2011","journal-title":"Acta Electronica Sinica"},{"article-title":"Research on code compression for embedded processors","year":"2007","author":"yang","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1992.697002"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1835420.1835424"},{"key":"ref23","first-page":"1","article-title":"A new code compression algorithm and its decompressor in FPGA-based hardware","author":"dias","year":"2013","journal-title":"Proc Symp Integrated Circuits and Systems Design (SBCCI)"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICIEV.2018.8641065"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/DICTA.2018.8615830"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/8948470\/09056512.pdf?arnumber=9056512","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T01:09:07Z","timestamp":1641949747000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9056512\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"references-count":37,"URL":"https:\/\/doi.org\/10.1109\/access.2020.2985501","relation":{},"ISSN":["2169-3536"],"issn-type":[{"type":"electronic","value":"2169-3536"}],"subject":[],"published":{"date-parts":[[2020]]}}}