{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,19]],"date-time":"2026-01-19T08:09:51Z","timestamp":1768810191366,"version":"3.49.0"},"reference-count":36,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2020]]},"DOI":"10.1109\/access.2020.2993989","type":"journal-article","created":{"date-parts":[[2020,5,12]],"date-time":"2020-05-12T22:58:27Z","timestamp":1589324307000},"page":"91405-91414","source":"Crossref","is-referenced-by-count":13,"title":["An Energy-Efficient and High Throughput in-Memory Computing Bit-Cell With Excellent Robustness Under Process Variations for Binary Neural Network"],"prefix":"10.1109","volume":"8","author":[{"given":"Gobinda","family":"Saha","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhewei","family":"Jiang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sanjay","family":"Parihar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cao","family":"Xi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jack","family":"Higman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2036-3960","authenticated-orcid":false,"given":"Muhammed","family":"Ahosan Ul Karim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2928043"},{"key":"ref32","article-title":"Batch normalization: Accelerating deep network training by reducing internal covariate shift","author":"ioffe","year":"2015","journal-title":"arXiv 1502 03167"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"},{"key":"ref30","article-title":"Automatic differentiation in PyTorch","author":"paszke","year":"2017","journal-title":"Proc NIPS Autodiff Workshop"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838029"},{"key":"ref35","article-title":"Learning multiple layers of features from tiny images","author":"krizhevsky","year":"2009"},{"key":"ref34","article-title":"Network in network","author":"lin","year":"2014","journal-title":"Proc Int Conf Learn Represent (ICLR)ICLR"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2019.2922889"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2642198"},{"key":"ref12","first-page":"496","article-title":"A 65 nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS\/W fully parallel product-sum operation for binary DNN edge processors","author":"khwa","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref13","first-page":"490","article-title":"A 42pJ\/decision 3.12TOPS\/W robust in-memory machine learning classifier with on-chip training","author":"gonugondla","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.2972528"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00040"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2014.6855225"},{"key":"ref17","first-page":"1","article-title":"Parallelizing SRAM arrays with customized bit-cell for binary neural networks","author":"liu","year":"2018","journal-title":"Proc 55th ACM\/ESDA\/IEEE Design Automat Conf (DAC)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2899730"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2907488"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1998.746322"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref27","first-page":"248c","article-title":"A ternary based bit scalable, 8.80 TOPS\/W CNN accelerator with many-core processing-in-memory architecture with 896 K synapses\/mm²","author":"okumura","year":"2019","journal-title":"Proc Symp VLSI Technol"},{"key":"ref3","first-page":"1097","article-title":"Imagenet classification with deep convolutional neural networks","author":"krizhevsky","year":"2012","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref6","article-title":"Binarized neural networks: Training deep neural networks with weights and activations constrained to +1 or ?1","author":"courbariaux","year":"2016","journal-title":"arXiv 1602 02830 [cs]"},{"key":"ref29","author":"lecun","year":"2010","journal-title":"MNIST Handwritten Digit Database"},{"key":"ref5","first-page":"10","article-title":"1.1 Computing’s energy problem (and what we can do about it)","author":"horowitz","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1126\/sciadv.1701329"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-46493-0_32"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"529","DOI":"10.1038\/nature14236","article-title":"Human-level control through deep reinforcement learning","volume":"518","author":"mnih","year":"2015","journal-title":"Nature"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310397"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"436","DOI":"10.1038\/nature14539","article-title":"Deep learning","volume":"521","author":"lecun","year":"2015","journal-title":"Nature"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342235"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662392"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510687"},{"key":"ref24","first-page":"242","article-title":"A 351TOPS\/W and 372.4GOPS compute-in-memory SRAM macro in 7 nm FinFET CMOS for machine-learning applications","author":"dong","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref23","first-page":"240","article-title":"A 28 nm 64 kb inference-training two-way transpose multibit 6T SRAM compute- in-memory macro for AI edge chips","author":"su","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICRC.2016.7738698"},{"key":"ref25","first-page":"246","article-title":"A 28 nm 64 kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips","author":"si","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/8948470\/09091590.pdf?arnumber=9091590","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,17]],"date-time":"2021-12-17T19:52:00Z","timestamp":1639770720000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9091590\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"references-count":36,"URL":"https:\/\/doi.org\/10.1109\/access.2020.2993989","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020]]}}}