{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,24]],"date-time":"2026-03-24T18:07:56Z","timestamp":1774375676651,"version":"3.50.1"},"reference-count":28,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"name":"Khalifa University of Science and Technology","award":["CIRA-2019-026"],"award-info":[{"award-number":["CIRA-2019-026"]}]},{"DOI":"10.13039\/501100004070","name":"System-On-Chip Center, Khalifa University of Science and Technology","doi-asserted-by":"publisher","award":["RC2-2018-020"],"award-info":[{"award-number":["RC2-2018-020"]}],"id":[{"id":"10.13039\/501100004070","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2020]]},"DOI":"10.1109\/access.2020.3004535","type":"journal-article","created":{"date-parts":[[2020,6,23]],"date-time":"2020-06-23T20:20:52Z","timestamp":1592943652000},"page":"117736-117745","source":"Crossref","is-referenced-by-count":11,"title":["FPGA-Based Memristor Emulator Circuit for Binary Convolutional Neural Networks"],"prefix":"10.1109","volume":"8","author":[{"given":"Mohammed F.","family":"Tolba","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9617-5080","authenticated-orcid":false,"given":"Yasmin","family":"Halawani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7185-0278","authenticated-orcid":false,"given":"Hani","family":"Saleh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6063-473X","authenticated-orcid":false,"given":"Baker","family":"Mohammad","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9600-8036","authenticated-orcid":false,"given":"Mahmoud","family":"Al-Qutayri","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2017.8203479"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001139"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2812800"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7527507"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2835572"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-017-0002-z"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1038\/nature06932"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2433536"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351696"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2018.2791458"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1063\/1.4931491"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2268376"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310393"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.3390\/make1010005"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1038\/s41565-018-0302-0"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1063\/1.3236573"},{"key":"ref8","first-page":"309","article-title":"Reducing read latency of phase change memory via early read and turbo read","author":"nair","year":"2015","journal-title":"Proc IEEE 21st Int Symp High Perform Comput Archit (HPCA)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1515\/ntrev-2015-0029"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1038\/ncomms12611"},{"key":"ref9","year":"2018","journal-title":"Introd Deep Learn with MATLAB"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7427997"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2882496"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref21","first-page":"1097","article-title":"Imagenet classification with deep convolutional neural networks","author":"krizhevsky","year":"2012","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref24","first-page":"4107","article-title":"Binarized neural networks","author":"hubara","year":"2016","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref23","first-page":"525","article-title":"XNOR-net: Imagenet classification using binary convolutional neural networks","author":"rastegari","year":"2016","journal-title":"Proc Eur Conf Comput Vis"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-01216-8_20"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2909317"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/8948470\/09123392.pdf?arnumber=9123392","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T01:08:38Z","timestamp":1641949718000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9123392\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/access.2020.3004535","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020]]}}}