{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,8]],"date-time":"2026-04-08T15:30:07Z","timestamp":1775662207238,"version":"3.50.1"},"reference-count":50,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2020]]},"DOI":"10.1109\/access.2020.3006732","type":"journal-article","created":{"date-parts":[[2020,7,2]],"date-time":"2020-07-02T20:27:41Z","timestamp":1593721661000},"page":"155306-155318","source":"Crossref","is-referenced-by-count":14,"title":["Improving Characteristics of LUT-Based Moore FSMs"],"prefix":"10.1109","volume":"8","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4941-3979","authenticated-orcid":false,"given":"Alexander","family":"Barkalov","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Larysa","family":"Titarenko","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9671-2800","authenticated-orcid":false,"given":"Slawomir","family":"Chmielewski","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","article-title":"SIS: A system for sequential circuit synthesis","author":"sentowich","year":"1992"},{"key":"ref38","first-page":"177","author":"kubatova","year":"2005","journal-title":"Design of Embedded Control System"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1007\/s10559-012-9410-2"},{"key":"ref32","volume":"38","author":"barkalov","year":"2015","journal-title":"Logic synthesis for FPGA-based Finite State Machines"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cds:20000671"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2406859"},{"key":"ref37","first-page":"109","article-title":"FEL&#x2013;code: FSM internal state encoding method","author":"kubatova","year":"2002","journal-title":"Proc 5th Int Workshop Boolean Problems"},{"key":"ref36","author":"micheli","year":"1994","journal-title":"Synthesis and Optimization of Digital Circuits"},{"key":"ref35","author":"baranov","year":"2008","journal-title":"Logic and System Design of Digital Systems"},{"key":"ref34","first-page":"151","article-title":"Design of mealy finite-state machines with the transformation of object codes","volume":"15","author":"barkalov","year":"2005","journal-title":"Int J Appl Math Comput Sci"},{"key":"ref28","author":"kam","year":"2010","journal-title":"Synthesis of Finite State Machines Functional Optimization"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3393-8"},{"key":"ref29","first-page":"502","article-title":"FPGA-based decomposition of Boolean functions: Algorithms and implementation","volume":"10","author":"nowicka","year":"1999","journal-title":"Adv Comput Syst"},{"key":"ref2","volume":"294","author":"sklyarov","year":"2014","journal-title":"Synthesis Optimation FPGA-based Systerm"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1002\/9780470987629"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.2478\/amcs-2018-0046"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-38295-7"},{"key":"ref24","author":"grout","year":"2011","journal-title":"Digital Systems Design with FPGAs and CPLDs"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887925"},{"key":"ref26","year":"2020","journal-title":"Virtex-5 family overview"},{"key":"ref25","year":"2020","journal-title":"Cyclone IV Device Handbook"},{"key":"ref50","first-page":"1","article-title":"Mixed encoding of collections of output variables for lut-based mealy fsms","volume":"28","author":"barkalov","year":"2018","journal-title":"J Circuits Syst Comput"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2000832.2000835"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1155\/2018\/6831901"},{"key":"ref40","year":"2020","journal-title":"LGSynth93"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1515\/amcs-2017-0015"},{"key":"ref13","author":"skliarova","year":"2012","journal-title":"Design of FPGA-based Circuits Using Hierarchical Finite State Machines"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-2692-6"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45716-X_36"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/329166.329183"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44614-1_76"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2731678"},{"key":"ref19","first-page":"916","article-title":"Saving power by mapping finite-state machines into embedded memory blocks in FPGAs","author":"tiwari","year":"2000","journal-title":"Proc Design Autom Test Eur Conf Exhib"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/12.954505"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-11961-4"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858306"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.231"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2654298"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2017.2746749"},{"key":"ref49","year":"2020","journal-title":"ABC System"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2010.5548558"},{"key":"ref46","author":"achasova","year":"1987","journal-title":"Synthesis Algorithms for Automata With PLAs"},{"key":"ref45","year":"2020","journal-title":"Vivado"},{"key":"ref48","first-page":"191","article-title":"Functional decomposition of combinational logic circuits with pkmin","volume":"2","author":"michalski","year":"2016","journal-title":"Trans on Journal of Elect Eng & Tech"},{"key":"ref47","year":"2020","journal-title":"DEMAIN"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-17545-9_5"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2004.07.004"},{"key":"ref44","year":"2020","journal-title":"Xilinx"},{"key":"ref43","first-page":"1","article-title":"Design of emb-based Moore fsms","volume":"26","author":"ko?opie?czyk","year":"2017","journal-title":"J Circuits Syst Comput"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/8948470\/09131767.pdf?arnumber=9131767","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,17]],"date-time":"2021-12-17T19:53:06Z","timestamp":1639770786000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9131767\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"references-count":50,"URL":"https:\/\/doi.org\/10.1109\/access.2020.3006732","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020]]}}}