{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,27]],"date-time":"2026-01-27T19:56:39Z","timestamp":1769543799044,"version":"3.49.0"},"reference-count":44,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"DOI":"10.13039\/501100002531","name":"Kyungpook National University Research Fund, 2019","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002531","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2020]]},"DOI":"10.1109\/access.2020.3015596","type":"journal-article","created":{"date-parts":[[2020,8,10]],"date-time":"2020-08-10T17:30:18Z","timestamp":1597080618000},"page":"149984-149998","source":"Crossref","is-referenced-by-count":15,"title":["Many-Tier Vertical GAAFET (V-FET) for Ultra-Miniaturized Standard Cell Designs Beyond 5 nm"],"prefix":"10.1109","volume":"8","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5243-4132","authenticated-orcid":false,"given":"Taigon","family":"Song","sequence":"first","affiliation":[{"name":"School of Electronics Engineering, Kyungpook National University (KNU), Daegu, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/MSPEC.2016.7607024"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1049\/el.2020.0266"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ICRAMET.2018.8683936"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/IITC-AMC.2017.7968983"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2015.7165874"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2019.2896362"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2016.7573409"},{"key":"ref36","year":"2018","journal-title":"Synopsys Quickcap NX"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2017.8268473"},{"key":"ref34","year":"2011","journal-title":"PDK 45nm Open Cell Library"},{"key":"ref10","year":"2020","journal-title":"Metrology Challenges for Gate-All-Around"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/DRC.2014.6872333"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2008.2005158"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1088\/0022-3727\/39\/21\/R01"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1126\/science.279.5348.208"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1021\/nl035162i"},{"key":"ref15","first-page":"1","article-title":"Lateral NWFET optimization for beyond 7nm nodes","author":"yakimets","year":"2015","journal-title":"Int Conf on IC Design and Technology (ICICDT)"},{"key":"ref16","year":"2017","journal-title":"IBM Research Alliance Builds New Transistor for 5 nm Technology"},{"key":"ref17","first-page":"196","article-title":"5 nm-gate nanowire FinFET","author":"yang","year":"2004","journal-title":"VLSI Symp Tech Dig"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIT.2017.7998183"},{"key":"ref19","first-page":"200","article-title":"A novel sub-50 nm multi-bridge-channel MOSFET (MBCFET) with extremely high performance","author":"lee","year":"2004","journal-title":"Symp VLSI Technol Dig Tech Papers"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2504729"},{"key":"ref4","year":"2018","journal-title":"Samsung Starts Mass Production of Chips Using Its 7 nm EUV Process Tech"},{"key":"ref27","first-page":"102","article-title":"Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5 nm and beyond technologies","author":"bao","year":"2014","journal-title":"Proc Euro Solid-State Device Res Conf (ESSDERC)"},{"key":"ref3","year":"2018","journal-title":"TSMC’s 7nm Technology"},{"key":"ref6","first-page":"67","article-title":"FinFET\/nanowire design for 5 nm\/3 nm technology nodes: Channel cladding and introducing a ‘bottleneck’ shape to remove performance bottleneck","author":"moroz","year":"2017","journal-title":"Proc IEEE Electron Devices Technol Manuf Conf (EDTM)"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2011.5873204"},{"key":"ref5","year":"2011","journal-title":"INTEL's Revolutionary 22-nm Transistor Technology"},{"key":"ref8","first-page":"58","article-title":"Sub-5nm all-around gate FinFET for ultimate scaling","author":"lee","year":"2006","journal-title":"Symp VLSI Technol Dig Tech Papers"},{"key":"ref7","first-page":"433","article-title":"Power-performance-area engineering of 5 nm nanowire library cells","author":"moroz","year":"2015","journal-title":"Proc Simulation Semiconductor Processes and Devices (SISPAD)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4418914"},{"key":"ref9","year":"2019","journal-title":"Limited EUV Manufacturing in 2019"},{"key":"ref1","first-page":"114","article-title":"Cramming more components onto integrated circuits","volume":"38","author":"moore","year":"1965","journal-title":"Electronics"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2008.4796805"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/S3S.2015.7333521"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2017.2769058"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/MSPEC.2018.8241736"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2013.6724557"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2018.8454841"},{"key":"ref23","year":"2019","journal-title":"Samsung Electronics’ Leadership in Advanced Foundry Technology Showcased With Latest Silicon Innovations and Ecosystem Platform"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1002\/spe.4380211102"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2017.2690598"},{"key":"ref43","article-title":"Spring embedders and force directed graph drawing algorithms","volume":"abs 1201s 3011","author":"kobourov","year":"2012","journal-title":"CoRR"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2019.2954537"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/8948470\/09163379.pdf?arnumber=9163379","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,1,27]],"date-time":"2026-01-27T05:59:56Z","timestamp":1769493596000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9163379\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"references-count":44,"URL":"https:\/\/doi.org\/10.1109\/access.2020.3015596","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020]]}}}