{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T16:43:42Z","timestamp":1774716222073,"version":"3.50.1"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"funder":[{"DOI":"10.13039\/100004358","name":"Samsung Electronics Company, Ltd., Device Solution","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100004358","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2020]]},"DOI":"10.1109\/access.2020.3030099","type":"journal-article","created":{"date-parts":[[2020,10,21]],"date-time":"2020-10-21T17:20:02Z","timestamp":1603300802000},"page":"187126-187139","source":"Crossref","is-referenced-by-count":22,"title":["An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache"],"prefix":"10.1109","volume":"8","author":[{"given":"Tae Hyun","family":"Kim","sequence":"first","affiliation":[]},{"given":"Hanwool","family":"Jeong","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4631-442X","authenticated-orcid":false,"given":"Juhyun","family":"Park","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0720-6821","authenticated-orcid":false,"given":"Hoonki","family":"Kim","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2752-3138","authenticated-orcid":false,"given":"Taejoong","family":"Song","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0757-2581","authenticated-orcid":false,"given":"Seong-Ook","family":"Jung","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2268543"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7169305"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2056110"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.907999"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2006.1696322"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/SOI.2006.284405"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2019.2906872"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250713"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2609386"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2415714"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1393921.1393954"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2294095"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2016.2521385"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/IITC-MAM.2015.7325600"},{"key":"ref3","first-page":"1","article-title":"Race to exascale: Opportunities and challenges","author":"sodani","year":"2011","journal-title":"Proc Keynote Annu IEEE\/ACM 44th Annu Int Symp Microarchitecture"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2017.2782740"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2295015"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2933463"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014208"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2479585"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"90","DOI":"10.1109\/LPE.2000.876763","article-title":"gated-v\/sub dd\/: a circuit technique to reduce leakage in deep-submicron cache memories","author":"powell","year":"2000","journal-title":"ISLPED 00 the 2000 International Symposium on Low Power Electronics and Design (Cat No 00TH8514) LPE-00"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870335"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2034764"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-1749-1"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2239320"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870334"},{"key":"ref24","first-page":"3.7.1","article-title":"A 14nm logic technology featuring $2^{nd}$\n-generation FinFET, air-gapped interconnects, self-aligned double patterning and a $0.0588~\\mu$\nm2 SRAM cell size","author":"natarajan","year":"2014","journal-title":"IEDM Tech Dig"},{"key":"ref23","first-page":"12t","article-title":"A 14 nm SoC platform technology featuring $2^{nd}$\n generation tri-gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 $\\mu{\\mathrm{ m}}$\n2 SRAM cells, optimized for low power, high performance and high density SoC products","author":"jan","year":"2015","journal-title":"Proc Symp VLSI Technol (VLSI-Technol )"},{"key":"ref26","first-page":"150t","article-title":"High sigma measurement of random threshold voltage variation in 14nm logic FinFET technology","author":"giles","year":"2015","journal-title":"Proc Symp VLSI Technol (VLSI-Technol )"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424366"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/8948470\/09229177.pdf?arnumber=9229177","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,17]],"date-time":"2021-12-17T19:56:58Z","timestamp":1639771018000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9229177\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"references-count":32,"URL":"https:\/\/doi.org\/10.1109\/access.2020.3030099","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020]]}}}