{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,10]],"date-time":"2026-01-10T07:41:34Z","timestamp":1768030894065,"version":"3.49.0"},"reference-count":59,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"name":"Serbian Ministry of Education, Science and Technological Development","award":["III44006(RZ62109)"],"award-info":[{"award-number":["III44006(RZ62109)"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2021]]},"DOI":"10.1109\/access.2021.3077539","type":"journal-article","created":{"date-parts":[[2021,5,4]],"date-time":"2021-05-04T20:58:43Z","timestamp":1620161923000},"page":"69346-69364","source":"Crossref","is-referenced-by-count":5,"title":["Migration in Hardware Transactional Memory on Asymmetric Multiprocessor"],"prefix":"10.1109","volume":"9","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3549-7056","authenticated-orcid":false,"given":"Zivojin","family":"Sustran","sequence":"first","affiliation":[{"name":"School of Electrical Engineering, University of Belgrade, Belgrade, Serbia"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2171-477X","authenticated-orcid":false,"given":"Jelica","family":"Protic","sequence":"additional","affiliation":[{"name":"School of Electrical Engineering, University of Belgrade, Belgrade, Serbia"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997876"},{"key":"ref38","first-page":"1","article-title":"AMD opteron shared memory MP systems","author":"ahmed","year":"2002","journal-title":"Proc 14th HotChips Symp"},{"key":"ref33","author":"greenhalgh","year":"2011"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253185"},{"key":"ref31","first-page":"385","year":"2018","journal-title":"64 and IA-32 Architectures Software Developer's Manual"},{"key":"ref30","author":"blundell","year":"2006","journal-title":"Unrestricted Transactional Memory Supporting I\/O and System Calls Within Transactions"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.35"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/40.491460"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/1128022.1128029"},{"key":"ref34","author":"chung","year":"2013","journal-title":"Heterogeneous Multi-Processing Solution of Exynos 5 Octa with ARM big LITTLE Technology (pdf)"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168903"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168901"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598134"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508274"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2856125"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-11515-8_5"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.13"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749718"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346204"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.54"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.41"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/362686.362692"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.379"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2006.6"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.14"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2012.32"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1145\/2751205.2751235"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2020.3031911"},{"key":"ref55","first-page":"1","article-title":"Survey of machine learning application in transactional memory","author":"vurdelja","year":"2020","journal-title":"Proceedings of Telecommunications Forum (TELFOR)"},{"key":"ref54","doi-asserted-by":"crossref","first-page":"187","DOI":"10.1016\/bs.adcom.2014.11.001","article-title":"Dual data cache systems","volume":"96","author":"sustran","year":"2015","journal-title":"Advances in Computers"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1816020"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-14720-8_6"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2018.2836418"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2018.2796077"},{"key":"ref40","article-title":"Simultaneous multi-threading implementation in POWER5","author":"kalla","year":"2003","journal-title":"Proc Conf Rec Hot Chips Symp"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237019"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2014.2357805"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1378533.1378564"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2755573.2755578"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2755573.2755612"},{"key":"ref17","first-page":"1","article-title":"HATS: Hardware-assisted transaction scheduler","volume":"153","author":"chen","year":"2020","journal-title":"Proc Leibniz Int Informat (LIPIcs)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2611462.2611482"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1294261.1294271"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151001"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/173682.165164"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654085"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485936"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2854038.2854047"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2020.3045279"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2008.209"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2016.12.011"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2008.4636089"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/800015.808204"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1016\/j.parco.2015.10.001"},{"key":"ref47","first-page":"385","year":"2016","journal-title":"Programming With Intel Transactional Synchronization Extensions Intel 64 and IA-32 Architectures Optimization Reference Manual"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.51"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref44","first-page":"1","article-title":"The Intel Pentium M processor: Microarchitecture and performance","volume":"7","author":"gochman","year":"2003","journal-title":"Intel Technol J"},{"key":"ref43","article-title":"Pentium processor data book","volume":"1","year":"1993","journal-title":"Pentium Processor User’s Manual"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/9312710\/09422791.pdf?arnumber=9422791","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,9,8]],"date-time":"2022-09-08T20:48:14Z","timestamp":1662670094000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9422791\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021]]},"references-count":59,"URL":"https:\/\/doi.org\/10.1109\/access.2021.3077539","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021]]}}}