{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,16]],"date-time":"2026-07-16T15:03:36Z","timestamp":1784214216967,"version":"3.55.0"},"reference-count":54,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2021]]},"DOI":"10.1109\/access.2021.3077977","type":"journal-article","created":{"date-parts":[[2021,5,6]],"date-time":"2021-05-06T19:50:40Z","timestamp":1620330640000},"page":"69210-69225","source":"Crossref","is-referenced-by-count":7,"title":["Metis: An Integrated Morphing Engine CPU to Protect Against Side Channel Attacks"],"prefix":"10.1109","volume":"9","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3480-486X","authenticated-orcid":false,"given":"Francesco","family":"Antognazza","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0840-6358","authenticated-orcid":false,"given":"Alessandro","family":"Barenghi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3812-5429","authenticated-orcid":false,"given":"Gerardo","family":"Pelosi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","first-page":"973","article-title":"Meltdown: Reading kernel memory from user space","author":"lipp","year":"2018","journal-title":"Proc 27th USENIX Secur Symp Secur (USENIX)"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2010.5513104"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2002.1030727"},{"key":"ref32","year":"2019"},{"key":"ref31","year":"2018"},{"key":"ref30","year":"2018"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48405-1_25"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00002"},{"key":"ref35","first-page":"1","author":"kiaei","year":"2020","journal-title":"Proc Cryptol ePrint Arch Rep"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-45146-4_27"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-011-0023-x"},{"key":"ref27","first-page":"55","article-title":"Good is not good enough&#x2014;Deriving optimal distinguishers from communication theory","volume":"8731","author":"heuser","year":"2014","journal-title":"Cryptographic Hardware and Embedded Systems&#x2014;CHES"},{"key":"ref29","year":"2010"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228376"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488833"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2996366.2996370"},{"key":"ref22","year":"2020","journal-title":"Coremark Benchmark Suite"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-85174-5_12"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2851486"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304037"},{"key":"ref26","doi-asserted-by":"crossref","first-page":"89","DOI":"10.1007\/978-3-319-54669-8_6","article-title":"Concealing secrets in embedded processors designs","volume":"10146","author":"gro\u00df","year":"2016","journal-title":"Smart Card Research and Advanced Applications"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/s00145-015-9224-2"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/MSP.2018.1331033"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/EUC.2011.62"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-43933-3_22"},{"key":"ref53","year":"2020","journal-title":"STM32F407\/417 Cortex-M4 Based Microcontroller Datasheet"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-01001-9_26"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2086696.2086699"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3281662"},{"key":"ref40","year":"2020","journal-title":"Ibex Documentation"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-28632-5_2"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2015.2407832"},{"key":"ref14","first-page":"13","article-title":"Template attacks","volume":"2523","author":"chari","year":"2002","journal-title":"Cryptographic Hardware and Embedded Systems&#x2014;CHES"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3178291.3178296"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-45931-8_9"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.14722\/ndss.2015.23264"},{"key":"ref18","first-page":"424","article-title":"27.3 EM and power SCA-resilient AES-256 in 65 nm CMOS through 350&#x00D7; current-domain signature attenuation","author":"das","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2017.7951799"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2430320"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2912924"},{"key":"ref6","first-page":"23","article-title":"PARAM: A microprocessor hardened for power side-channel attack resistance","author":"arsath","year":"2020","journal-title":"Proc IEEE Int Symp Hardw Oriented Secur Trust (HOST)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00059"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2926389"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-48324-4_30"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-15031-9_28"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196112"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-23951-9_14"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/MSEC.2020.2990495"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00041"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-41284-4_11"},{"key":"ref42","year":"2020","journal-title":"OpenTitan Documentation"},{"key":"ref41","year":"2020","journal-title":"Ibex RISC-V Core"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44499-8_19"},{"key":"ref43","year":"2020","journal-title":"OpenTitan Github Repository"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/9312710\/09424552.pdf?arnumber=9424552","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,17]],"date-time":"2021-12-17T19:57:36Z","timestamp":1639771056000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9424552\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021]]},"references-count":54,"URL":"https:\/\/doi.org\/10.1109\/access.2021.3077977","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021]]}}}