{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,10]],"date-time":"2026-03-10T09:06:38Z","timestamp":1773133598514,"version":"3.50.1"},"reference-count":28,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"DOI":"10.13039\/501100003977","name":"Israel Science Foundation","doi-asserted-by":"publisher","award":["2511\/20"],"award-info":[{"award-number":["2511\/20"]}],"id":[{"id":"10.13039\/501100003977","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003977","name":"Israel Science Foundation","doi-asserted-by":"publisher","award":["1266\/20"],"award-info":[{"award-number":["1266\/20"]}],"id":[{"id":"10.13039\/501100003977","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Israel Innovation Authority in the frame of the Magneton Program"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2021]]},"DOI":"10.1109\/access.2021.3088991","type":"journal-article","created":{"date-parts":[[2021,6,14]],"date-time":"2021-06-14T20:05:02Z","timestamp":1623701102000},"page":"91764-91776","source":"Crossref","is-referenced-by-count":5,"title":["Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads"],"prefix":"10.1109","volume":"9","author":[{"given":"Yoav","family":"Weizman","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1410-4746","authenticated-orcid":false,"given":"Robert","family":"Giterman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Oron","family":"Chertkow","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Maoz","family":"Wicentowski","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5591-5799","authenticated-orcid":false,"given":"Itamar","family":"Levi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ilan","family":"Sever","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ishai","family":"Kehati","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3101-9551","authenticated-orcid":false,"given":"Osnat","family":"Keren","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alexander","family":"Fish","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2019.8902622"},{"key":"ref11","article-title":"Secured memory","author":"giterman","year":"2020"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2020.i1.152-174"},{"key":"ref13","year":"2015","journal-title":"International Technology Roadmap for Semiconductors—2015 Edition"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/SISW.2003.10004"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CMC.2009.31"},{"key":"ref16","first-page":"122","article-title":"Design solutions for securing SRAM cell against power analysis","author":"ro\u017ei?","year":"2012","journal-title":"Proc IEEE Int Symp Hardw -Oriented Secur Trust"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/WAC.2006.375932"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2009.4977309"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2278350"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2015.7231274"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2019411"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1002\/0471200611"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2019.i2.293-317"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2452371"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2840132"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2359720"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-21476-4"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2886175"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-011-0006-y"},{"key":"ref20","first-page":"242","article-title":"A 28 nm SoC with a 1.2 GHz 568 nJ\/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications","author":"whatmough","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1166\/jno.2015.1843"},{"key":"ref21","first-page":"458","article-title":"A process-variation-tolerant dual-power-supply SRAM with 0.179 ?m² cell in 40 nm CMOS using level-programmable wordline driver","author":"hirabayashi","year":"2009","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref24","first-page":"1","article-title":"45 nm bit-interleaving differential 10T low leakage FinFET based SRAM with column-wise write access control","author":"gupta","year":"2018","journal-title":"Proc IEEE Int Symp Defect Fault Tolerance VLSI Syst (DFT)"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/NUICONE.2015.7449596"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.3005338"},{"key":"ref25","article-title":"Pseudo-asynchronous digital circuit design","author":"itamar","year":"2020"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/9312710\/09453841.pdf?arnumber=9453841","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,17]],"date-time":"2021-12-17T19:56:34Z","timestamp":1639770994000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9453841\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/access.2021.3088991","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021]]}}}