{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,8]],"date-time":"2025-09-08T06:48:22Z","timestamp":1757314102241,"version":"3.37.3"},"reference-count":46,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2021]]},"DOI":"10.1109\/access.2021.3103200","type":"journal-article","created":{"date-parts":[[2021,8,9]],"date-time":"2021-08-09T20:25:56Z","timestamp":1628540756000},"page":"114120-114134","source":"Crossref","is-referenced-by-count":5,"title":["Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage Assignment"],"prefix":"10.1109","volume":"9","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7113-5197","authenticated-orcid":false,"given":"Mohsen","family":"Raji","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Reza","family":"Mahmoudi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5391-383X","authenticated-orcid":false,"given":"Behnam","family":"Ghavami","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Saeed","family":"Keshavarzi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/SMACD.2017.7981556"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2902961.2903013"},{"key":"ref33","first-page":"326","article-title":"TILOS: A posynomial programming approach to transistor sizing","author":"fishburn","year":"1985","journal-title":"Proc Best ICCAD"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3177864"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2020.113617"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-018-5707-z"},{"key":"ref37","first-page":"117","article-title":"P?²? CLRAF: An pre-and post-silicon cooperated circuit lifetime reliability analysis framework","author":"jin","year":"2010","journal-title":"Proc 19th IEEE Asian Test Symp"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1007\/978-81-322-2508-9_5"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-4078-9_6"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907047"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2017.2780083"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2011.6081439"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS50870.2020.9159733"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2020.2987946"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672007"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.3390\/technologies8020025"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2011.03.004"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.3003471"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-019-05772-5"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2020.103713"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2846629"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/MIXDES.2015.7208525"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2040125"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2018.2799739"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2898006"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-019-05788-x"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2015.7314433"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2013.2281986"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICSE49846.2020.9166861"},{"key":"ref7","first-page":"236","article-title":"Incorporating effects of process, voltage, and temperature variation in BTI model for circuit design","author":"krishnappa","year":"2010","journal-title":"Proc IEEE Latin Amer Symp Circuits Syst"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.840407"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2012.6241887"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.982424"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2019.2933998"},{"key":"ref20","first-page":"476","article-title":"A novel NBTI-aware chip remaining lifetime prediction framework using machine learning","author":"chen","year":"2021","journal-title":"Proc Int Symp Quality Electronic Design (ISQED)"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/ETC.1989.36234"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2010.5784734"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2011.5770699"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1016\/j.ins.2018.03.042"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2013.6509663"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1016\/j.cor.2017.03.016"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2011.5993802"},{"journal-title":"Predictive Technology Model (PTM)","year":"2005","key":"ref44"},{"key":"ref26","first-page":"1","article-title":"Aadam: A fast, accurate, and versatile aging-aware cell library delay model using feed-forward neural network","author":"ebrahimipour","year":"2020","journal-title":"Proc 39th Int Conf Comput -Aided Design"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-6163-0"},{"key":"ref25","doi-asserted-by":"crossref","first-page":"1976","DOI":"10.3390\/electronics9111976","article-title":"A learning-based framework for circuit path level NBTI degradation prediction","volume":"9","author":"aiguo","year":"2020","journal-title":"Electronics"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/9312710\/09509021.pdf?arnumber=9509021","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,17]],"date-time":"2021-12-17T19:57:24Z","timestamp":1639771044000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9509021\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021]]},"references-count":46,"URL":"https:\/\/doi.org\/10.1109\/access.2021.3103200","relation":{},"ISSN":["2169-3536"],"issn-type":[{"type":"electronic","value":"2169-3536"}],"subject":[],"published":{"date-parts":[[2021]]}}}