{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,14]],"date-time":"2026-02-14T10:29:45Z","timestamp":1771064985130,"version":"3.50.1"},"reference-count":34,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"DOI":"10.13039\/501100003329","name":"Ministerio de Industria y Competitividad of Spain","doi-asserted-by":"publisher","award":["TIN2017-89951-P (BootTimeIoT)"],"award-info":[{"award-number":["TIN2017-89951-P (BootTimeIoT)"]}],"id":[{"id":"10.13039\/501100003329","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100008530","name":"European Regional Development Fund","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100008530","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100009042","name":"VI Plan Propio de Investigacion y Transferencia de la Universidad de Sevilla","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100009042","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2021]]},"DOI":"10.1109\/access.2021.3132188","type":"journal-article","created":{"date-parts":[[2021,12,1]],"date-time":"2021-12-01T20:34:01Z","timestamp":1638390841000},"page":"161383-161394","source":"Crossref","is-referenced-by-count":3,"title":["An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation"],"prefix":"10.1109","volume":"9","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8963-0855","authenticated-orcid":false,"given":"German","family":"Cano-Quiveu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paulino","family":"Ruiz-De-Clavijo-Vazquez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5092-6042","authenticated-orcid":false,"given":"Manuel J.","family":"Bellido-Diaz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Guerrero-Martos","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7543-5082","authenticated-orcid":false,"given":"Julian","family":"Viejo-Cortes","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jorge","family":"Juan-Chico","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","year":"2020","journal-title":"Nexys 4 DDR [Reference Digilentinc]"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2010045"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-23951-9_21"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-74735-2_31"},{"key":"ref34","year":"2010","journal-title":"7 series fpgas data sheet Overview (ds180)"},{"key":"ref10","year":"2020","journal-title":"Integrated Logic Analyzer (ILA)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSE.2006.365129"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TLA.2016.7459587"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MIPRO.2014.6859555"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2012.02.005"},{"key":"ref15","year":"2021","journal-title":"PicoBlaze 8-bit Microcontroller"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2016.7857170"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ELNANO50318.2020.9088878"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3059941"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2017.8292096"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2907717"},{"key":"ref4","year":"2020","journal-title":"PyRTL by UCSBarchlab"},{"key":"ref27","year":"2021","journal-title":"GitHub&#x2014;Germancq\/IPCores"},{"key":"ref3","year":"2020","journal-title":"Myhdl"},{"key":"ref6","year":"2018","journal-title":"Vivado High-Level Synthesis"},{"key":"ref29","year":"2020","journal-title":"GitHub&#x2014;Olofk\/Fusesoc Package Manager and Build Abstraction Tool for FPGA\/ASIC Development"},{"key":"ref5","year":"2020","journal-title":"Introduction&#x2014;COCOTB 1 1 Documentation"},{"key":"ref8","author":"stroud","year":"2002","journal-title":"A Designer's Guide to Built-In Self-Test"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.5121\/ijesa.2012.2204"},{"key":"ref2","article-title":"Quantifying FPGA verification effectiveness","volume":"16","author":"foster","year":"2020","journal-title":"Verification Horizons"},{"key":"ref9","year":"0","journal-title":"Virtual Input\/Output v3 0 LogiCORE IP Product Guide Vivado Design Suite"},{"key":"ref1","year":"2020","journal-title":"IoT Infrastructure Technology & Connectivity Explained&#x2014;Business Insider"},{"key":"ref20","year":"2020","journal-title":"Jenkins"},{"key":"ref22","year":"2020","journal-title":"Docker Empowering app development for developers"},{"key":"ref21","year":"2020","journal-title":"GitHub Where the world builds software"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.2997610"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/SPL.2019.8714377"},{"key":"ref26","year":"2005","journal-title":"SD Specifications Part 1 Physical Layer Specification V1 10"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2017.07.007"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/9312710\/09632568.pdf?arnumber=9632568","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,3,14]],"date-time":"2022-03-14T21:46:13Z","timestamp":1647294373000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9632568\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021]]},"references-count":34,"URL":"https:\/\/doi.org\/10.1109\/access.2021.3132188","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021]]}}}