{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T20:21:28Z","timestamp":1740169288987,"version":"3.37.3"},"reference-count":50,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2022]]},"DOI":"10.1109\/access.2022.3162070","type":"journal-article","created":{"date-parts":[[2022,3,24]],"date-time":"2022-03-24T21:38:44Z","timestamp":1648157924000},"page":"36152-36165","source":"Crossref","is-referenced-by-count":0,"title":["Improving Characteristics of FSMs With Mixed Codes of Outputs"],"prefix":"10.1109","volume":"10","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4941-3979","authenticated-orcid":false,"given":"Alexander","family":"Barkalov","sequence":"first","affiliation":[{"name":"Faculty of Computer, Electrical and Control Engineering, Institute of Metrology, Electronics and Computer Science, University of Zielona G&#x00F3;ra, Zielona Gora, Poland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Larysa","family":"Titarenko","sequence":"additional","affiliation":[{"name":"Faculty of Computer, Electrical and Control Engineering, Institute of Metrology, Electronics and Computer Science, University of Zielona G&#x00F3;ra, Zielona Gora, Poland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9671-2800","authenticated-orcid":false,"given":"Slawomir","family":"Chmielewski","sequence":"additional","affiliation":[{"name":"Institute of Science and Technology, State University of Applied Sciences in G&#x0142;og&#x00F3;w, Glogow, Poland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4027-7541","authenticated-orcid":false,"given":"Kamil","family":"Mielcarek","sequence":"additional","affiliation":[{"name":"Faculty of Computer, Electrical and Control Engineering, Institute of Metrology, Electronics and Computer Science, University of Zielona G&#x00F3;ra, Zielona Gora, Poland"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-60488-2"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-04708-9"},{"volume-title":"Logic and System Design of Digital Systems","year":"2008","author":"Baranov","key":"ref3"},{"volume-title":"Synthesis and Optimization of Digital Circuits","year":"1994","author":"Micheli","key":"ref4"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1002\/9780470987629"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/b978-0-7506-8397-5.x0001-3"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-36166-1"},{"key":"ref8","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-030-38295-7","volume-title":"Synthesis for FPGA-Based Control Units","volume":"636","author":"Barkalov","year":"2020"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1142\/s0218126619501317"},{"volume-title":"Field-Programmable Gate Array Technology","year":"2012","author":"Trimberger","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1002\/9780470127896"},{"volume-title":"Design of FPGA-based circuits using Hierarchical Finite State Machines","year":"2012","author":"Skliarova","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.3390\/computation7040063"},{"volume-title":"X. FPGAs","year":"2021","key":"ref14"},{"volume-title":"Cyclone IV Device Handbook","year":"2021","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1561\/1000000005"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3393-8"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2878187"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887925"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2895206"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1515\/amcs-2017-0015"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1007\/0-387-28327-7"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174272"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.2478\/amcs-2018-0046"},{"issue":"4","key":"ref25","doi-asserted-by":"crossref","first-page":"745","DOI":"10.34768\/amcs-2020-0055","article-title":"Improving characteristics of LUT-based mealy FSMs","volume":"30","author":"Barkalov","year":"2020","journal-title":"Int. J. Appl. Math. Comput. Sci."},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.3006732"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1515\/bpasts-2017-0036"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2018.02.009"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2068716.2068720"},{"volume-title":"ABC System","year":"2021","key":"ref30"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2898230"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2004.07.004"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-7518-8"},{"volume-title":"Vivado","year":"2021","key":"ref34"},{"volume-title":"Quartus Prime","year":"2021","key":"ref35"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1134\/s1064230712010091"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44614-1_76"},{"article-title":"SIS: A system for sequential circuit synthesis","year":"1992","author":"Sentowich","key":"ref38"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/4.364440"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45716-X_36"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1985.1270123"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1134\/s1064226912060113"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2016.08.001"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1017\/s0305004100028322"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1979.1675352"},{"volume-title":"Synthesis Algorithms for Automata With PLAs","year":"1987","author":"Achasova","key":"ref46"},{"article-title":"International workshop on logic synthesis benchmark suite (LGSynth93)","year":"1993","author":"McElvain","key":"ref47"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1269007"},{"volume-title":"VC709 Evaluation Board for the Virtex-7 FPGA User Guide","year":"2019","key":"ref49"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.2988379"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/9668973\/09740626.pdf?arnumber=9740626","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,9,20]],"date-time":"2024-09-20T22:53:03Z","timestamp":1726872783000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9740626\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022]]},"references-count":50,"URL":"https:\/\/doi.org\/10.1109\/access.2022.3162070","relation":{},"ISSN":["2169-3536"],"issn-type":[{"type":"electronic","value":"2169-3536"}],"subject":[],"published":{"date-parts":[[2022]]}}}