{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,15]],"date-time":"2026-07-15T22:30:50Z","timestamp":1784154650056,"version":"3.55.0"},"reference-count":304,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"DOI":"10.13039\/100000028","name":"SAFARI Research Group\u2019s industrial partners, especially ASML, Facebook, Google, Huawei, Intel, Microsoft, VMware, Xilinx, the ETH Future Computing Laboratory, and Semiconductor Research Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100016263","name":"University Research Board of the American University of Beirut","doi-asserted-by":"publisher","award":["URB-AUB-103951-25960"],"award-info":[{"award-number":["URB-AUB-103951-25960"]}],"id":[{"id":"10.13039\/501100016263","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100005411","name":"Foundation for Education and European Culture","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100005411","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2022]]},"DOI":"10.1109\/access.2022.3174101","type":"journal-article","created":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T19:40:40Z","timestamp":1652211640000},"page":"52565-52608","source":"Crossref","is-referenced-by-count":153,"title":["Benchmarking a New Paradigm: Experimental Analysis and Characterization of a Real Processing-in-Memory System"],"prefix":"10.1109","volume":"10","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6514-1571","authenticated-orcid":false,"given":"Juan","family":"Gomez-Luna","sequence":"first","affiliation":[{"name":"Department of Information Technology and Electrical Engineering, ETH Zürich, Zürich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Izzat El","family":"Hajj","sequence":"additional","affiliation":[{"name":"Department of Computer Science, American University of Beirut, Beirut, Lebanon"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ivan","family":"Fernandez","sequence":"additional","affiliation":[{"name":"Department of Information Technology and Electrical Engineering, ETH Zürich, Zürich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0162-4547","authenticated-orcid":false,"given":"Christina","family":"Giannoula","sequence":"additional","affiliation":[{"name":"Department of Information Technology and Electrical Engineering, ETH Zürich, Zürich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Geraldo F.","family":"Oliveira","sequence":"additional","affiliation":[{"name":"Department of Information Technology and Electrical Engineering, ETH Zürich, Zürich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0075-2312","authenticated-orcid":false,"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"Department of Information Technology and Electrical Engineering, ETH Zürich, Zürich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref275","doi-asserted-by":"publisher","DOI":"10.1137\/1.9781611972740.43"},{"key":"ref274","doi-asserted-by":"publisher","DOI":"10.1145\/2020408.2020579"},{"key":"ref277","year":"2017","journal-title":"NVIDIA Titan V"},{"key":"ref276","doi-asserted-by":"publisher","DOI":"10.1098\/rspb.1998.0303"},{"key":"ref271","doi-asserted-by":"publisher","DOI":"10.1109\/InPar.2012.6339606"},{"key":"ref270","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2015.2412549"},{"key":"ref273","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-5041-2940-4_9"},{"key":"ref170","doi-asserted-by":"publisher","DOI":"10.1145\/3309697.3331482"},{"key":"ref272","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2012.319"},{"key":"ref172","doi-asserted-by":"publisher","DOI":"10.1145\/2833179.2833184"},{"key":"ref171","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2414456"},{"key":"ref174","doi-asserted-by":"crossref","first-page":"80","DOI":"10.1038\/nature06932","article-title":"The missing memristor found","volume":"453","author":"strukov","year":"2008","journal-title":"Nature"},{"key":"ref173","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557176"},{"key":"ref176","doi-asserted-by":"publisher","DOI":"10.1145\/1785414.1785441"},{"key":"ref175","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2012.2190369"},{"key":"ref178","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555759"},{"key":"ref177","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"ref168","year":"2013","journal-title":"High-bandwidth Memory (HBM) DRAM"},{"key":"ref169","doi-asserted-by":"publisher","DOI":"10.1145\/2832911"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00036"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2020.2990599"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446095"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358260"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00011"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00026"},{"key":"ref267","doi-asserted-by":"crossref","first-page":"17","DOI":"10.1098\/rstl.1858.0002","article-title":"II. A memoir on the theory of matrices","volume":"148","author":"cayley","year":"1858","journal-title":"Philos Trans Roy Soc London"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446749"},{"key":"ref268","author":"hungerford","year":"2012","journal-title":"Abstract Algebra An Introduction"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196029"},{"key":"ref269","doi-asserted-by":"publisher","DOI":"10.1145\/2555243.2555266"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123977"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00033"},{"key":"ref288","article-title":"Simple DRAM and virtual memory abstractions to enable highly efficient memory systems","author":"seshadri","year":"2016"},{"key":"ref287","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2017.7975269"},{"key":"ref286","doi-asserted-by":"publisher","DOI":"10.1145\/2555243.2555253"},{"key":"ref285","author":"merrill","year":"2015","journal-title":"CUDA UnBound (CUB) library"},{"key":"ref284","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657065"},{"key":"ref181","doi-asserted-by":"publisher","DOI":"10.1145\/2669365"},{"key":"ref283","doi-asserted-by":"publisher","DOI":"10.1016\/B978-0-12-385963-1.00026-5"},{"key":"ref180","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2070050"},{"key":"ref282","year":"2021","journal-title":"CUDA Samples V 11 2"},{"key":"ref281","year":"2011","journal-title":"Intel 64 and IA-32 architectures software developer's manual"},{"key":"ref280","year":"2016","journal-title":"NVIDIA system management interface program"},{"key":"ref185","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2016.7753257"},{"key":"ref184","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3110993"},{"key":"ref183","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2020.3029600"},{"key":"ref182","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378661"},{"key":"ref189","article-title":"The processing using memory paradigm: In-DRAM bulk copy, initialization, bitwise AND and OR","author":"seshadri","year":"2016","journal-title":"arXiv 1610 09603"},{"key":"ref188","article-title":"In-DRAM bulk bitwise execution engine","author":"seshadri","year":"2019","journal-title":"arXiv 1905 09822"},{"key":"ref187","doi-asserted-by":"publisher","DOI":"10.1145\/3155287"},{"key":"ref186","doi-asserted-by":"publisher","DOI":"10.1109\/FPL50879.2020.00014"},{"key":"ref28","article-title":"RowClone: Accelerating data movement and initialization using DRAM","author":"seshadri","year":"2018","journal-title":"arXiv 1805 03502"},{"key":"ref27","first-page":"185","article-title":"RowClone: Fast and Energy-Efficient in-DRAM Bulk Data Copy and Initialization","author":"vivek seshadri","year":"2013","journal-title":"2013 46th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)"},{"key":"ref179","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.24"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/3299874.3317984"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/514191.514197"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00040"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.21"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2014.6855225"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322257"},{"key":"ref278","year":"2017","journal-title":"Nvidia tesla v100 gpu architecture"},{"key":"ref26","article-title":"Buddy-RAM: Improving the performance and efficiency of bulk bitwise operations using DRAM","author":"seshadri","year":"2016","journal-title":"arXiv 1611 09988"},{"key":"ref279","year":"2014","journal-title":"RAPL Power Meter"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124544"},{"key":"ref293","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358329"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0970"},{"key":"ref292","doi-asserted-by":"publisher","DOI":"10.1145\/2818950.2818953"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927095"},{"key":"ref295","doi-asserted-by":"publisher","DOI":"10.1109\/BIBM.2016.7822732"},{"key":"ref294","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00089"},{"key":"ref297","doi-asserted-by":"publisher","DOI":"10.1145\/3243176.3243187"},{"key":"ref296","doi-asserted-by":"publisher","DOI":"10.1109\/BIBM49941.2020.9313351"},{"key":"ref299","doi-asserted-by":"publisher","DOI":"10.1145\/3508041"},{"key":"ref298","first-page":"1","article-title":"Processing in storage class memory","author":"nider","year":"2020","journal-title":"Proc HotStorage"},{"key":"ref154","doi-asserted-by":"publisher","DOI":"10.1145\/3078505.3078533"},{"key":"ref153","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056057"},{"key":"ref156","doi-asserted-by":"publisher","DOI":"10.1145\/2896377.2901453"},{"key":"ref155","doi-asserted-by":"publisher","DOI":"10.1145\/3078505.3078590"},{"key":"ref150","doi-asserted-by":"publisher","DOI":"10.1145\/2591971.2592000"},{"key":"ref291","article-title":"Mitigating edge machine learning inference bottlenecks: An empirical study on accelerating Google edge models","author":"boroumand","year":"2021","journal-title":"arXiv 2103 00768"},{"key":"ref152","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123945"},{"key":"ref290","article-title":"Polynesia: Enabling effective hybrid transactional\/analytical databases with specialized hardware\/software co-design","author":"boroumand","year":"2021","journal-title":"arXiv 2103 00798"},{"key":"ref151","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2016.30"},{"key":"ref146","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"ref147","doi-asserted-by":"publisher","DOI":"10.1109\/SP40000.2020.00085"},{"key":"ref148","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00037"},{"key":"ref149","first-page":"255","article-title":"The reach profiler (reaper) enabling the mitigation of DRAM retention failures via profiling at aggressive conditions","author":"patel","year":"2017","journal-title":"Proc ISCA"},{"key":"ref289","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00052"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00081"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.3013728"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD50377.2020.00035"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00031"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342278"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927083"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357122"},{"key":"ref52","first-page":"1718","article-title":"Memristor based computation-in-memory architecture for data-intensive applications","author":"hamdioui","year":"2015","journal-title":"Proc DATE"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2945617"},{"key":"ref167","year":"2014","journal-title":"HMC specification 2 0"},{"key":"ref166","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480061"},{"key":"ref165","first-page":"1198","article-title":"Uncovering in-DRAM RowHammer protection mechanisms: A new methodology, custom RowHammer patterns, and implications","author":"hassan","year":"2021","journal-title":"Proc MICRO"},{"key":"ref164","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480069"},{"key":"ref163","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.58"},{"key":"ref162","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750392"},{"key":"ref161","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2010.5703348"},{"key":"ref160","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950392"},{"key":"ref4","article-title":"A workload and programming ease driven perspective of processing-in-memory","author":"ghose","year":"2019","journal-title":"arXiv 1907 12947"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2019.2934048"},{"key":"ref6","author":"mutlu","year":"2017","journal-title":"Processing Data Where it Makes Sense Enabling in-Memory Computation"},{"key":"ref5","article-title":"Enabling the adoption of processing-in-memory: Challenges, mechanisms, future research directions","author":"ghose","year":"2018","journal-title":"arXiv 1802 00320"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173177"},{"key":"ref159","doi-asserted-by":"publisher","DOI":"10.1145\/1998582.1998590"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3323476"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2282132"},{"key":"ref157","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835946"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2014.6983056"},{"key":"ref158","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.57"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2357292"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2014.06.006"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2011.6081389"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001139"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2018.8465706"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898064"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317764"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196009"},{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446059"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.22"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056040"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001140"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.46"},{"key":"ref77","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783764"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001154"},{"key":"ref75","first-page":"1","article-title":"3D-stacked memory-side acceleration: Accelerator and system design","author":"guo","year":"2014","journal-title":"Proc WoNDP"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001159"},{"key":"ref79","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001178"},{"key":"ref60","article-title":"GRIM-filter: Fast seed filtering in read mapping using emerging memory technologies","author":"kim","year":"2017","journal-title":"arXiv 1708 04329"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750385"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1186\/s12864-018-4460-0"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750386"},{"key":"ref304","article-title":"Benchmarking a new paradigm: An experimental analysis of a real processing-in-memory architecture","author":"g\u00f3mez-luna","year":"2021","journal-title":"arXiv 2105 03814"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322266"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2016.2577557"},{"key":"ref66","article-title":"LazyPIM: Efficient support for cache coherence in processing-in-memory architectures","author":"boroumand","year":"2017","journal-title":"arXiv 1706 03162"},{"key":"ref301","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.3011265"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317867"},{"key":"ref300","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2857044"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783753"},{"key":"ref303","doi-asserted-by":"publisher","DOI":"10.1109\/IGSC54211.2021.9651614"},{"key":"ref69","first-page":"2069","article-title":"JAFAR: Near-data processing for databases","author":"babarinsa","year":"2015","journal-title":"Proc SIGMOD"},{"key":"ref302","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref197","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237032"},{"key":"ref198","year":"2018","journal-title":"Introduction to UPMEM PIM Processing-in-memory (PIM) on DRAM Accelerator (White Paper)"},{"key":"ref199","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2019.8875680"},{"key":"ref193","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.2998456"},{"key":"ref194","doi-asserted-by":"publisher","DOI":"10.1109\/ICRC.2018.8638612"},{"key":"ref195","doi-asserted-by":"publisher","DOI":"10.1109\/ICRC.2017.8123649"},{"key":"ref196","doi-asserted-by":"publisher","DOI":"10.1145\/3394885.3431554"},{"key":"ref95","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358256"},{"key":"ref94","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS47924.2020.00076"},{"key":"ref190","doi-asserted-by":"publisher","DOI":"10.1016\/bs.adcom.2017.04.004"},{"key":"ref93","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00053"},{"key":"ref191","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2434872"},{"key":"ref92","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2821565"},{"key":"ref192","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304049"},{"key":"ref91","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080233"},{"key":"ref90","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037702"},{"key":"ref98","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480133"},{"key":"ref99","article-title":"PLUTo: Enabling massively parallel computation in DRAM via lookup tables","author":"dinis ferreira","year":"2021","journal-title":"arXiv 2104 07699"},{"key":"ref96","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927081"},{"key":"ref97","doi-asserted-by":"publisher","DOI":"10.1109\/ICRC.2017.8123667"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.1145\/3087556.3087582"},{"key":"ref81","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.42"},{"key":"ref84","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.54"},{"key":"ref83","doi-asserted-by":"publisher","DOI":"10.1145\/2686875"},{"key":"ref80","doi-asserted-by":"publisher","DOI":"10.1145\/3126908.3126965"},{"key":"ref89","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750397"},{"key":"ref85","doi-asserted-by":"publisher","DOI":"10.1145\/2967938.2967940"},{"key":"ref86","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844483"},{"key":"ref87","doi-asserted-by":"publisher","DOI":"10.1145\/2600212.2600213"},{"key":"ref88","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2013.6670336"},{"key":"ref200","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2005.1499974"},{"key":"ref101","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2015.230"},{"key":"ref100","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00078"},{"key":"ref209","author":"thornton","year":"1970","journal-title":"Design of a Computer The Control Data 6600"},{"key":"ref203","first-page":"148","article-title":"8.3 A 3 GHz ARM neoverse n1 CPU in 7 nm FinFET for infrastructure applications","author":"christy","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref204","first-page":"52","article-title":"3.2 Zen: A next-generation high-performance $\\times86$\n core","author":"singh","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref201","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744819"},{"key":"ref202","first-page":"264","article-title":"A fully integrated multi-CPU, GPU and memory controller 32 nm processor","author":"yuffe","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref207","first-page":"39","article-title":"A pipelined, shared resource MIMD computer","author":"smith","year":"1978","journal-title":"Proc ICPP"},{"key":"ref208","doi-asserted-by":"publisher","DOI":"10.1117\/12.932535"},{"key":"ref205","author":"mutlu","year":"2020","journal-title":"Lecture 18C Fine-Grained Multithreading"},{"key":"ref206","author":"hennessy","year":"2012","journal-title":"Computer Architecture—A Quantitative Approach Instruction-level Parallelism and Its Exploitation"},{"key":"ref211","author":"hennessy","year":"2012","journal-title":"Computer Architecture—A Quantitative Approach Data-level Parallelism in Vector SIMD and GPU Architectures"},{"key":"ref210","author":"mutlu","year":"2020","journal-title":"Lecture 19 SIMD Processors"},{"key":"ref212","doi-asserted-by":"crossref","first-page":"1901","DOI":"10.1109\/PROC.1966.5273","article-title":"very high-speed computing systems","volume":"54","author":"flynn","year":"1966","journal-title":"Proceedings of the IEEE"},{"key":"ref213","year":"2021","journal-title":"UPMEM User Manual Version 2021 1 0"},{"key":"ref214","year":"2022","journal-title":"PrIM Benchmark Suite"},{"key":"ref215","doi-asserted-by":"publisher","DOI":"10.1145\/1498765.1498785"},{"key":"ref216","doi-asserted-by":"publisher","DOI":"10.1201\/EBK1439811924"},{"key":"ref217","doi-asserted-by":"publisher","DOI":"10.1145\/1465482.1465560"},{"key":"ref218","doi-asserted-by":"publisher","DOI":"10.1145\/42411.42415"},{"key":"ref219","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1993.393370"},{"key":"ref220","doi-asserted-by":"publisher","DOI":"10.1109\/MM.1997.612174"},{"key":"ref222","author":"kim","year":"2014","journal-title":"Computing Handbook Computer Science and Software Engineering Memory Systems"},{"key":"ref221","article-title":"Design of the RISC-V instruction set architecture","author":"waterman","year":"2016"},{"key":"ref229","year":"2019","journal-title":"Intel Xeon Silver 4215 Processor"},{"key":"ref228","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830820"},{"key":"ref227","year":"2020","journal-title":"UPMEM Website"},{"key":"ref226","year":"2012","journal-title":"DDR4 SDRAM Standard"},{"key":"ref225","author":"mutlu","year":"2020","journal-title":"Lecture 4A Memory Systems Solution Directions"},{"key":"ref224","author":"mutlu","year":"2020","journal-title":"Lecture 3B Memory Systems Challenges and Opportunities"},{"key":"ref223","author":"mutlu","year":"2020","journal-title":"Lecture 2B Data Retention and Memory Refresh"},{"key":"ref127","article-title":"Accelerating weather prediction using near-memory reconfigurable fabric","author":"singh","year":"2021","journal-title":"ACM Trans Reconfigurable Technol Syst"},{"key":"ref126","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2021.3088396"},{"key":"ref125","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-021-03661-3"},{"key":"ref124","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00080"},{"key":"ref129","doi-asserted-by":"publisher","DOI":"10.1109\/PACT52795.2021.00019"},{"key":"ref128","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3110993"},{"key":"ref130","doi-asserted-by":"publisher","DOI":"10.1109\/PACT52795.2021.00019"},{"key":"ref133","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485928"},{"key":"ref134","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2013.6582088"},{"key":"ref131","article-title":"Casper: Accelerating stencil computation using near-cache processing","author":"denzler","year":"2021","journal-title":"arXiv 2112 14216"},{"key":"ref132","article-title":"Co-architecting controllers and DRAM to enhance DRAM process scaling","volume":"14","author":"kang","year":"2014","journal-title":"The Memory Forum"},{"key":"ref232","author":"mutlu","year":"2020","journal-title":"Lecture 20 Graphics Processing Units"},{"key":"ref233","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-04818-0_3"},{"key":"ref230","year":"2017","journal-title":"Intel Xeon Silver 4110 Processor"},{"key":"ref231","author":"jodin","year":"2020","journal-title":"UPMEM personal communication"},{"key":"ref239","doi-asserted-by":"publisher","DOI":"10.1145\/1188455.1188677"},{"key":"ref238","year":"2021","journal-title":"LLVM Compiler Project"},{"key":"ref235","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2004.1281665"},{"key":"ref234","year":"2021","journal-title":"Software Development Kit (SDK)"},{"key":"ref237","article-title":"Memory bandwidth and machine balance in current high performance computers","author":"mccalpin","year":"1995","journal-title":"IEEE Comput Soc Tech Committee Comput Archit"},{"key":"ref236","year":"2020","journal-title":"Compiler Explorer"},{"key":"ref136","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927156"},{"key":"ref135","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665726"},{"key":"ref138","first-page":"19","article-title":"Research problems and opportunities in memory systems","volume":"1","author":"mutlu","year":"2014","journal-title":"Supercomputing Frontiers and Innovations"},{"key":"ref137","doi-asserted-by":"publisher","DOI":"10.1145\/3219617.3219661"},{"key":"ref139","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00059"},{"key":"ref140","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2915318"},{"key":"ref141","doi-asserted-by":"publisher","DOI":"10.1109\/SP40000.2020.00090"},{"key":"ref142","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2018.00051"},{"key":"ref143","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337161"},{"key":"ref2","article-title":"A modern primer on processing in memory","author":"mutlu","year":"2021","journal-title":"arXiv 2012 03112"},{"key":"ref144","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4939-2163-8_6"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2019.01.009"},{"key":"ref145","doi-asserted-by":"publisher","DOI":"10.1147\/rd.462.0187"},{"key":"ref241","year":"2017","journal-title":"Intel Xeon Processor E3-1225 V6"},{"key":"ref242","year":"2020","journal-title":"Intel Advisor"},{"key":"ref243","doi-asserted-by":"crossref","first-page":"135","DOI":"10.1145\/567806.567807","article-title":"An updated set of basic linear algebra subprograms (BLAS)","volume":"28","author":"blackford","year":"2002","journal-title":"ACM Trans Math Softw"},{"key":"ref244","doi-asserted-by":"publisher","DOI":"10.1137\/1.9780898718003"},{"key":"ref240","year":"2011","journal-title":"Intel Advanced Vector Extensions Programming Reference"},{"key":"ref248","doi-asserted-by":"crossref","first-page":"324","DOI":"10.1109\/TSE.1985.232223","article-title":"translating sql into relational algebra: optimization, semantics, and equivalence of sql queries","volume":"se 11","author":"ceri","year":"1985","journal-title":"IEEE Transactions on Software Engineering"},{"key":"ref247","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358286"},{"key":"ref246","doi-asserted-by":"publisher","DOI":"10.1145\/2751205.2751209"},{"key":"ref245","doi-asserted-by":"publisher","DOI":"10.1137\/1.9780898718003"},{"key":"ref249","doi-asserted-by":"publisher","DOI":"10.1109\/12.42122"},{"key":"ref109","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2015.2409732"},{"key":"ref108","doi-asserted-by":"publisher","DOI":"10.1145\/2818950.2818986"},{"key":"ref107","doi-asserted-by":"publisher","DOI":"10.1145\/3132402.3132434"},{"key":"ref106","doi-asserted-by":"publisher","DOI":"10.1145\/3240302.3240428"},{"key":"ref105","doi-asserted-by":"publisher","DOI":"10.1145\/3357526.3357571"},{"key":"ref104","article-title":"Combining emulation and simulation to evaluate a near memory key\/value lookup accelerator","author":"landgraf","year":"2021","journal-title":"arXiv 2105 06594"},{"key":"ref103","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7527507"},{"key":"ref102","doi-asserted-by":"publisher","DOI":"10.1109\/54.748803"},{"key":"ref111","doi-asserted-by":"publisher","DOI":"10.1145\/2742854.2742863"},{"key":"ref112","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2435018"},{"key":"ref110","article-title":"Compiling for the active memory cube","author":"jacob","year":"2016"},{"key":"ref250","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2015.30"},{"key":"ref251","doi-asserted-by":"publisher","DOI":"10.1145\/2442516.2442539"},{"key":"ref254","doi-asserted-by":"publisher","DOI":"10.1109\/ICDM.2018.00099"},{"key":"ref255","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-96868-6_25"},{"key":"ref252","doi-asserted-by":"publisher","DOI":"10.1007\/BF00264289"},{"key":"ref253","doi-asserted-by":"publisher","DOI":"10.1109\/ICDM.2016.0179"},{"key":"ref257","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837289"},{"key":"ref256","author":"kirk","year":"2017","journal-title":"Programming Massively Parallel Processors Parallel Patterns Graph Search"},{"key":"ref259","doi-asserted-by":"publisher","DOI":"10.1016\/0022-2836(70)90057-4"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2013.6704670"},{"key":"ref258","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-17943-7_117"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1969.222754"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1970.5008902"},{"key":"ref13","first-page":"41","article-title":"The NON-VON database machine: A brief overview","volume":"4","author":"shaw","year":"1981","journal-title":"IEEE Database Eng Bull"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.1994.108"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/2.375174"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/40.592312"},{"key":"ref118","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2021.3065448"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694774"},{"key":"ref117","author":"mutlu","year":"2022","journal-title":"Computer Architecture (Fall 2021)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378608"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.21236\/ADA419598"},{"key":"ref119","article-title":"PiDRAM: A holistic end-to-end FPGA-based framework for Processing-in-DRAM","author":"olgun","year":"2021","journal-title":"arXiv 2111 00082"},{"key":"ref114","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2020.3004543"},{"key":"ref113","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2014.55"},{"key":"ref116","author":"mutlu","year":"2022","journal-title":"Computer Architecture (Fall 2021)"},{"key":"ref115","author":"mutlu","year":"2022","journal-title":"Exploring the Processing-in-Memory Paradigm for Future Computing Systems (Fall 2021)"},{"key":"ref120","first-page":"1","article-title":"A 1 ynm 1.25 V 8 Gb, 16 Gb\/s\/pin GDDR6-based accelerator-in-memory supporting 1TFLOPS MAC operation and various activation functions for deep-learning applications","author":"lee","year":"2022","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref121","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2021.3097700"},{"key":"ref122","first-page":"350","article-title":"25.4 A 20 nm 6 GB function-in-memory dram, based on HBM2 with a 1.2TFLOPS programmable computing unit using bank-level parallelism, for machine learning applications","author":"kwon","year":"2021","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref123","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00013"},{"key":"ref260","doi-asserted-by":"publisher","DOI":"10.1007\/s00138-012-0443-3"},{"key":"ref261","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-24685-5_1"},{"key":"ref262","first-page":"70","article-title":"Optimizing parallel reduction in CUDA","volume":"2","author":"harris","year":"2007","journal-title":"NVIDIA Developer Technology"},{"key":"ref263","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2019.8661187"},{"key":"ref264","author":"kirk","year":"2017","journal-title":"Programming Massively Parallel Processors Parallel Patterns Prefix Sum An Introduction to Work Efficiency in Parallel Algorithms"},{"key":"ref265","article-title":"Efficient parallel scan algorithms for GPUs","author":"sengupta","year":"2008"},{"key":"ref266","doi-asserted-by":"publisher","DOI":"10.1145\/1375527.1375559"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/9668973\/09771457.pdf?arnumber=9771457","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,27]],"date-time":"2022-06-27T21:01:32Z","timestamp":1656363692000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9771457\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022]]},"references-count":304,"URL":"https:\/\/doi.org\/10.1109\/access.2022.3174101","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022]]}}}