{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,10]],"date-time":"2026-04-10T21:35:10Z","timestamp":1775856910781,"version":"3.50.1"},"reference-count":190,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"name":"University of Trieste and the Abdus Salam International Centre for Theoretical Physics"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2022]]},"DOI":"10.1109\/access.2022.3201107","type":"journal-article","created":{"date-parts":[[2022,8,23]],"date-time":"2022-08-23T19:42:05Z","timestamp":1661283725000},"page":"90429-90455","source":"Crossref","is-referenced-by-count":48,"title":["High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks"],"prefix":"10.1109","volume":"10","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7688-6248","authenticated-orcid":false,"given":"Romina Soledad","family":"Molina","sequence":"first","affiliation":[{"name":"Dipartimento di Ingegneria e Architettura (DIA), Universit&#x00E0; degli Studi di Trieste, Trieste, Italy"}]},{"given":"Veronica","family":"Gil-Costa","sequence":"additional","affiliation":[{"name":"CONICET, Universidad Nacional de San Luis, San Luis, Argentina"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5483-3388","authenticated-orcid":false,"given":"Maria Liz","family":"Crespo","sequence":"additional","affiliation":[{"name":"Multidisciplinary Laboratory (MLab), The Abdus Salam International Centre for Theoretical Physics, Trieste, Italy"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4494-3743","authenticated-orcid":false,"given":"Giovanni","family":"Ramponi","sequence":"additional","affiliation":[{"name":"Dipartimento di Ingegneria e Architettura (DIA), Universit&#x00E0; degli Studi di Trieste, Trieste, Italy"}]}],"member":"263","reference":[{"key":"ref1","article-title":"A survey of FPGA-based robotic computing","author":"Wan","year":"2020","journal-title":"arXiv:2009.06034"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/j.cosrev.2018.01.002"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2017.2705434"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3289185"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2513673"},{"key":"ref6","volume-title":"Vivado Design Suite User Guide: High-Level Synthesis. UG-902","year":"2020"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2110592"},{"key":"ref8","volume-title":"Intel High Level Synthesis Compiler, Best Practices Guide. UG-20107","year":"2020"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950423"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645550"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1155\/2012\/649057"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.5479\/ads\/bib\/2013ivoa.spec.0329g"},{"key":"ref13","first-page":"13","article-title":"Models for parallel computing: Review and perspectives","volume":"24","author":"Kessler","year":"2007","journal-title":"Mitteilungen Gesellschaft f\u00fcr Informatik e.V., Parallel-Algorithmen und Rechnerstrukturen"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2943570"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3494534"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.3024098"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3003276"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2018.00143"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3357375"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.3012084"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/800152.804898"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/800133.804339"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/72935.72953"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/79173.79181"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1016\/j.jcss.2010.06.012"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1101499.1101504"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-05057-3_12"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/PDP2018.2018.00098"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2103736.2103743"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1134\/S0361768819080103"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1080\/21642583.2020.1822947"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1007\/s10994-021-06064-w"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.3390\/sym9090197"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ICDM.2019.00198"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/HiPC.2015.34"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/155332.155333"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/CLUSTR.2007.4629232"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1006\/jpdc.1997.1346"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/71.920589"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ISPAN.1999.778942"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45591-4_162"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/CCGRID.2010.60"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-35606-3_25"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/EMPDP.1999.746640"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/1498765.1498785"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.5547"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-80126-7_35"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1155\/2013\/428078"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-17248-4_7"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/DLS51937.2020.00007"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1007\/s11704-007-0016-1"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1145\/28395.28428"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1007\/BF01185206"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1080\/10637199608915543"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1504\/IJHPCN.2004.007571"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/CISIS.2007.49"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1007\/s00607-019-00780-x"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1145\/3478684.3479261"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1007\/s11036-022-01985-9"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00086"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1038\/s41598-021-90221-7"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00061"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1155\/2020\/7095048"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/ICM.2009.5418618"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2878129"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1016\/j.future.2017.01.021"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2017.8091091"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1109\/EmbeddedSys.2014.6953049"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2011.55"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1016\/j.swevo.2012.06.003"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2012.02.015"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2035579"},{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1109\/VDAT.2009.5158106"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2004.1281665"},{"key":"ref75","volume-title":"Clang","year":"2022"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1007\/s11390-020-9414-8"},{"key":"ref77","doi-asserted-by":"publisher","DOI":"10.1109\/iccad.2017.8203809"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240815"},{"key":"ref79","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689087"},{"key":"ref80","doi-asserted-by":"publisher","DOI":"10.1007\/s11554-017-0722-3"},{"key":"ref81","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW52791.2021.00029"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.1109\/tpds.2020.3039409"},{"key":"ref83","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-17227-5_17"},{"key":"ref84","doi-asserted-by":"publisher","DOI":"10.1109\/ICCE48956.2021.9352106"},{"key":"ref85","doi-asserted-by":"publisher","DOI":"10.1109\/ICCT46805.2019.8947168"},{"key":"ref86","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-44534-8_10"},{"key":"ref87","doi-asserted-by":"publisher","DOI":"10.1145\/3264817"},{"key":"ref88","doi-asserted-by":"publisher","DOI":"10.5815\/ijieeb.2012.05.07"},{"key":"ref89","doi-asserted-by":"publisher","DOI":"10.23919\/ConTEL52528.2021.9495970"},{"key":"ref90","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD46524.2019.00059"},{"key":"ref91","doi-asserted-by":"publisher","DOI":"10.1109\/UEMCON47517.2019.8992929"},{"key":"ref92","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2017.44"},{"key":"ref93","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203844"},{"key":"ref94","doi-asserted-by":"publisher","DOI":"10.1145\/3078155.3078163"},{"key":"ref95","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1987.13876"},{"key":"ref96","article-title":"Theoretical model of computation and algorithms for FPGA-based hardware accelerators","author":"Hora","year":"2018","journal-title":"arXiv:1807.03611"},{"key":"ref97","doi-asserted-by":"publisher","DOI":"10.1145\/2068716.2068722"},{"key":"ref98","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062251"},{"key":"ref99","doi-asserted-by":"publisher","DOI":"10.1109\/FPL53798.2021.00022"},{"key":"ref100","doi-asserted-by":"publisher","DOI":"10.1109\/PMBS51919.2020.00007"},{"key":"ref101","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00069"},{"key":"ref102","doi-asserted-by":"publisher","DOI":"10.1109\/RECONFIG.2017.8279804"},{"key":"ref103","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446058"},{"key":"ref104","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1204375"},{"key":"ref105","doi-asserted-by":"publisher","DOI":"10.1145\/1929943.1929947"},{"key":"ref106","first-page":"157","article-title":"Exploiting loop-array dependencies to accelerate the design space exploration with high level synthesis","volume-title":"Proc. Design, Autom. Test Eur. Conf. Exhib. (DATE)","author":"Pham"},{"key":"ref107","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2014.6983050"},{"key":"ref108","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2008.4541637"},{"key":"ref109","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2014.2320556"},{"key":"ref110","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174255"},{"key":"ref111","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2016.7929519"},{"key":"ref112","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2017.8009208"},{"key":"ref113","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577358"},{"key":"ref114","doi-asserted-by":"publisher","DOI":"10.1145\/3427377"},{"key":"ref115","first-page":"39","article-title":"IronMan: GNN-assisted design space exploration in high-level synthesis via reinforcement learning","volume-title":"Proc. Great Lakes Symp. VLSI (GLSVLSI)","author":"Wu"},{"key":"ref116","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3111761"},{"key":"ref117","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2017.05.014"},{"key":"ref118","first-page":"1","article-title":"A CAD-based methodology to optimize HLS code via the roofline model","volume-title":"Proc. 39th Int. Conf. Comput.-Aided Design","author":"Siracusa"},{"key":"ref119","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44614-1_58"},{"key":"ref120","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3012750"},{"key":"ref121","doi-asserted-by":"publisher","DOI":"10.1145\/3126566"},{"key":"ref122","first-page":"918","article-title":"Adaptive threshold non-Pareto elimination: Re-thinking machine learning for system level design space exploration on FPGAs","volume-title":"Proc. Design, Automat. Test Eur. Conf. Exhib. (DATE)","author":"Meng"},{"key":"ref123","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2019.01.010"},{"key":"ref124","doi-asserted-by":"publisher","DOI":"10.1145\/3380446.3430636"},{"key":"ref125","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00029"},{"key":"ref126","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317754"},{"key":"ref127","doi-asserted-by":"publisher","DOI":"10.1109\/SBCCI50935.2020.9189899"},{"key":"ref128","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415657"},{"key":"ref129","doi-asserted-by":"publisher","DOI":"10.1109\/NorCAS51424.2020.9265138"},{"key":"ref130","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898040"},{"key":"ref131","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT47387.2019.00063"},{"key":"ref132","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927161"},{"key":"ref133","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2912916"},{"key":"ref134","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2018.2794068"},{"key":"ref135","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2018.00040"},{"key":"ref136","doi-asserted-by":"publisher","DOI":"10.1145\/3511472"},{"key":"ref137","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.20"},{"key":"ref138","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3288756"},{"key":"ref139","volume-title":"PowerTool MAXPOWERTOOL002 Quick Start Guide","year":"2014"},{"key":"ref140","volume-title":"USB Interface Adapter Evaluation Module. User\u2019s Guide","year":"2006"},{"key":"ref141","volume-title":"Xilinx Power Estimator User Guide. UG-440 (v2021.2)","year":"2021"},{"key":"ref142","volume-title":"Intel FPGA Power and Thermal Calculator User Guide","year":"2021"},{"key":"ref143","doi-asserted-by":"publisher","DOI":"10.1145\/3129789"},{"key":"ref144","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942119"},{"key":"ref145","doi-asserted-by":"publisher","DOI":"10.1109\/ISWCS.2016.7600969"},{"key":"ref146","doi-asserted-by":"publisher","DOI":"10.1145\/3203217.3204462"},{"key":"ref147","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2019.2935052"},{"key":"ref148","doi-asserted-by":"publisher","DOI":"10.1007\/s11277-018-5938-4"},{"key":"ref149","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2008.4517885"},{"key":"ref150","doi-asserted-by":"publisher","DOI":"10.1007\/s11277-018-5927-7"},{"key":"ref151","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2018.2840686"},{"key":"ref152","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240816"},{"key":"ref153","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC47756.2020.9045442"},{"key":"ref154","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774682"},{"key":"ref155","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853196"},{"key":"ref156","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2018.08.004"},{"key":"ref157","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-46117-5_33"},{"key":"ref158","doi-asserted-by":"publisher","DOI":"10.3390\/electronics9081275"},{"key":"ref159","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS49936.2021.00116"},{"key":"ref160","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2016.12.015"},{"key":"ref161","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-44534-8_18"},{"key":"ref162","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2018.00026"},{"key":"ref163","article-title":"A living review of machine learning for particle physics","author":"Feickert","year":"2021","journal-title":"arXiv:2102.02770"},{"key":"ref164","article-title":"Applications and techniques for fast machine learning in science","author":"Deiana","year":"2021","journal-title":"arXiv:2110.13041"},{"key":"ref165","doi-asserted-by":"publisher","DOI":"10.1146\/annurev-fluid-010719-060214"},{"key":"ref166","doi-asserted-by":"publisher","DOI":"10.1145\/3186332"},{"key":"ref167","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2019.8916327"},{"key":"ref168","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC43674.2020.9286149"},{"key":"ref169","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2019.00028"},{"key":"ref170","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7428073"},{"key":"ref171","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2018.03.007"},{"key":"ref172","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.2994256"},{"key":"ref173","doi-asserted-by":"publisher","DOI":"10.3906\/elk-1706-222"},{"key":"ref174","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2018.00052"},{"key":"ref175","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.3025550"},{"key":"ref176","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2897634"},{"key":"ref177","article-title":"FPDeep: Scalable acceleration of CNN training on deeply-pipelined FPGA clusters","author":"Geng","year":"2019","journal-title":"arXiv:1901.01007"},{"key":"ref178","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2016.7760779"},{"key":"ref179","doi-asserted-by":"publisher","DOI":"10.1145\/3490422.3502359"},{"key":"ref180","doi-asserted-by":"publisher","DOI":"10.3390\/electronics9122200"},{"key":"ref181","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021791"},{"key":"ref182","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293915"},{"key":"ref183","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2016.010"},{"key":"ref184","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00032"},{"key":"ref185","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203894"},{"key":"ref186","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196109"},{"key":"ref187","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375306"},{"key":"ref188","article-title":"A graph deep learning framework for high-level synthesis design space exploration","author":"Ferretti","year":"2021","journal-title":"arXiv:2111.14767"},{"key":"ref189","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2015.2505723"},{"key":"ref190","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2013.50"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/9668973\/09864576.pdf?arnumber=9864576","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,1]],"date-time":"2024-02-01T12:37:17Z","timestamp":1706791037000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9864576\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022]]},"references-count":190,"URL":"https:\/\/doi.org\/10.1109\/access.2022.3201107","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022]]}}}