{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,13]],"date-time":"2026-03-13T12:00:49Z","timestamp":1773403249607,"version":"3.50.1"},"reference-count":54,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"funder":[{"name":"Institute of Information and Communications Technology Planning and Evaluation (IITP) Grant"},{"name":"Korean Government through the Ministry of Science and ICT (MSIT)","award":["2021-0-00863"],"award-info":[{"award-number":["2021-0-00863"]}]},{"name":"Korean Government through the Ministry of Science and ICT (MSIT)","award":["2021-0-00479"],"award-info":[{"award-number":["2021-0-00479"]}]},{"DOI":"10.13039\/501100003725","name":"National Research and Development Program through the National Research Foundation of Korea","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100014188","name":"MSIT","doi-asserted-by":"crossref","award":["2020M3H2A1076786"],"award-info":[{"award-number":["2020M3H2A1076786"]}],"id":[{"id":"10.13039\/501100014188","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100003836","name":"IC Design Education Center (IDEC), South Korea","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003836","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2022]]},"DOI":"10.1109\/access.2022.3201525","type":"journal-article","created":{"date-parts":[[2022,8,25]],"date-time":"2022-08-25T19:33:55Z","timestamp":1661456035000},"page":"89769-89780","source":"Crossref","is-referenced-by-count":10,"title":["SEC-BADAEC: An Efficient ECC With No Vacancy for Strong Memory Protection"],"prefix":"10.1109","volume":"10","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9716-7031","authenticated-orcid":false,"given":"Yuseok","family":"Song","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8320-7001","authenticated-orcid":false,"given":"Sangjae","family":"Park","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6537-2065","authenticated-orcid":false,"given":"Michael B.","family":"Sullivan","sequence":"additional","affiliation":[{"name":"NVIDIA, Santa Clara, CA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1587-0677","authenticated-orcid":false,"given":"Jungrae","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Semiconductor Systems Engineering, Sungkyunkwan University, Suwon, South Korea"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2011.5958246"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2017.2711034"},{"key":"ref3","first-page":"24","article-title":"System level design considerations for soft error mitigation","volume-title":"Proc. IEEE CPMT Chapter SCV Soft Error Rate Workshop","author":"Evans"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2017.26"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2012.13"},{"key":"ref6","first-page":"1","article-title":"Feng Shui of supercomputer memory: Positional effects in DRAM and SRAM faults","volume-title":"Proc. Int. Conf. High Perform. Comput., Netw., Storage Anal.","author":"Sridharan"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694348"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.57"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480111"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056025"},{"key":"ref11","volume-title":"SK Hynix details DDR5-6400","author":"Shilov","year":"2019"},{"key":"ref12","article-title":"Micron\u00ae DDR5 SDRAM: New features","author":"Rooney","year":"2019"},{"key":"ref13","volume-title":"DDR5 SDRAM, JESD79-5A","year":"2021"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2016.54"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/23.903783"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3132402.3132410"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.30"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2353799"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.58"},{"key":"ref20","volume-title":"Semiconductor memory devices and methods of operating semiconductor memory devices","author":"Sangyun","year":"2021"},{"key":"ref21","volume-title":"BIOS and Kernel Developer\u2019s Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors","year":"2013"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/PRDC.2013.18"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2503210.2503243"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/isscc19947.2020.9063110"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1147\/rd.144.0395"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1137\/0108018"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9781139172769"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1950.tb00463.x"},{"issue":"3","key":"ref29","doi-asserted-by":"crossref","first-page":"221","DOI":"10.1023\/A:1008394205999","article-title":"On perfect codes and related concepts","volume":"22","author":"Ahlswede","year":"2001","journal-title":"Designs, Codes Cryptogr."},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2012.36"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/icecs.2008.4674921"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2011.3"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2013.6653601"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2010.5699220"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/3194554.3194570"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2766361"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.40"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISoC.2011.6081647"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2012.2232671"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2150989"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2014.6962069"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485928"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1063\/1.363119"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.58"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3061349"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665726"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/1897816.1897844"},{"key":"ref48","volume-title":"TN-40\u201307: Calculating Memory Power for DDR4 SDRAM","year":"2017"},{"key":"ref49","first-page":"11","article-title":"Co-architecting controllers and DRAM to enhance DRAM process scaling","volume-title":"Proc. Memory Forum","volume":"14","author":"Kang"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485929"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2005.860675"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2011.5784599"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2007.908147"},{"key":"ref54","volume-title":"PCI Express Base Specification Revision 6.0","year":"2022"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/9668973\/09866743.pdf?arnumber=9866743","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,1]],"date-time":"2024-02-01T12:50:57Z","timestamp":1706791857000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9866743\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022]]},"references-count":54,"URL":"https:\/\/doi.org\/10.1109\/access.2022.3201525","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022]]}}}