{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T16:24:30Z","timestamp":1774628670210,"version":"3.50.1"},"reference-count":46,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100003816","name":"Huawei Technologies Research and Development (U.K.) Ltd","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003816","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2022]]},"DOI":"10.1109\/access.2022.3222346","type":"journal-article","created":{"date-parts":[[2022,11,14]],"date-time":"2022-11-14T21:42:06Z","timestamp":1668462126000},"page":"120702-120713","source":"Crossref","is-referenced-by-count":8,"title":["A General Framework for Accelerator Management Based on ISA Extension"],"prefix":"10.1109","volume":"10","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3737-683X","authenticated-orcid":false,"given":"Elham","family":"Cheshmikhani","sequence":"first","affiliation":[{"name":"Department of Information Engineering and Mathematics, University of Siena, Siena, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4998-0092","authenticated-orcid":false,"given":"Biagio","family":"Peccerillo","sequence":"additional","affiliation":[{"name":"Department of Information Engineering and Mathematics, University of Siena, Siena, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andrea","family":"Mondelli","sequence":"additional","affiliation":[{"name":"Huawei Technologies Research & Development (UK) Limited, Cambridge, U.K"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sandro","family":"Bartolini","sequence":"additional","affiliation":[{"name":"Department of Information Engineering and Mathematics, University of Siena, Siena, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/3422667"},{"key":"ref38","year":"2022","journal-title":"The Linux Kernel Documentation"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00016"},{"key":"ref32","article-title":"ISA extensions in the snitch processor for signal processing","author":"mazzola","year":"2021"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001179"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-71817-0_9"},{"key":"ref37","year":"2001","journal-title":"Linux Device Drivers"},{"key":"ref36","article-title":"The gem5 simulator: Version 20.0+","author":"lowe-power","year":"2020","journal-title":"arXiv 2007 03152"},{"key":"ref35","author":"waterman","year":"2020","journal-title":"The RISC-V instruction set manual volume i Unprivileged ISA"},{"key":"ref34","year":"2009","journal-title":"Arm1176JZF-S Technical Reference Manual"},{"key":"ref10","year":"2020","journal-title":"NVIDIA AMPERE GA102 GPU ARCHITECTURE"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2846688"},{"key":"ref11","year":"2019","journal-title":"RDNA Architecture"},{"key":"ref12","year":"2020","journal-title":"Cloud tensor processing units (tpus)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3284557.3284563"},{"key":"ref14","first-page":"2055","author":"dongarra","year":"2011","journal-title":"Top500"},{"key":"ref15","year":"2022","journal-title":"AMBA overview"},{"key":"ref16","year":"2022","journal-title":"DE-CIX Website"},{"key":"ref17","year":"2022","journal-title":"Compute Express Link The Breakthrough CPU-to-Device Interconnect"},{"key":"ref18","year":"2021","journal-title":"CUDA C Programming Guide"},{"key":"ref19","year":"2012","journal-title":"The OpenCL Specification Version 1 2"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080255"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228512"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00015"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.50"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3126560"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISVDAT.2015.7208116"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744794"},{"key":"ref8","year":"2020","journal-title":"Huawei Kirin 990—Rethink Evolution"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3361682"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2022.102561"},{"key":"ref9","year":"2020","journal-title":"A14 Bionic FAQ What You Need to Know About Apple’s 5 nm Processor"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3282307"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref20","article-title":"IntersectX: An efficient accelerator for graph mining","author":"rao","year":"2020","journal-title":"arXiv 2012 10848"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/3065386"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/EIT.2007.4374484"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-78610-8_20"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.58"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2020.i4.239-280"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2025952"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/EIConRus.2017.7910596"},{"key":"ref26","article-title":"Tightly coupling the PicoRV32 RISC-V processor with custom logic accelerators via a generic interface","author":"todd","year":"2021"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS45731.2020.9180579"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/9668973\/09950481.pdf?arnumber=9950481","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,11]],"date-time":"2024-12-11T02:12:24Z","timestamp":1733883144000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9950481\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022]]},"references-count":46,"URL":"https:\/\/doi.org\/10.1109\/access.2022.3222346","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022]]}}}