{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,16]],"date-time":"2026-04-16T01:44:08Z","timestamp":1776303848472,"version":"3.50.1"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"DOI":"10.13039\/501100001863","name":"New Energy and Industrial Technology Development Organization","doi-asserted-by":"publisher","award":["JPNP16007"],"award-info":[{"award-number":["JPNP16007"]}],"id":[{"id":"10.13039\/501100001863","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2023]]},"DOI":"10.1109\/access.2023.3236974","type":"journal-article","created":{"date-parts":[[2023,1,16]],"date-time":"2023-01-16T19:16:27Z","timestamp":1673896587000},"page":"5701-5713","source":"Crossref","is-referenced-by-count":21,"title":["An Exploration of State-of-the-Art Automation Frameworks for FPGA-Based DNN Acceleration"],"prefix":"10.1109","volume":"11","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4746-9992","authenticated-orcid":false,"given":"Fumio","family":"Hamanaka","sequence":"first","affiliation":[{"name":"Tokyo Institute of Technology, Tokyo, Japan"}]},{"given":"Takashi","family":"Odan","sequence":"additional","affiliation":[{"name":"Tokyo Institute of Technology, Tokyo, Japan"}]},{"given":"Kenji","family":"Kise","sequence":"additional","affiliation":[{"name":"Tokyo Institute of Technology, Tokyo, Japan"}]},{"given":"Thiem Van","family":"Chu","sequence":"additional","affiliation":[{"name":"Tokyo Institute of Technology, Tokyo, Japan"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM51124.2021.00018"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021741"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2018.00014"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FPL53798.2021.00011"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2018.00286"},{"issue":"1","key":"ref6","first-page":"1","article-title":"Quantized neural networks: Training neural networks with low precision weights and activations","volume":"18","author":"Hubara","year":"2017","journal-title":"J. Mach. Learn. Res."},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021744"},{"key":"ref8","volume-title":"Vitis-AI: Vitis AI is Xilinx\u2019s Development Stack for AI Inference on Xilinx Hardware Platforms, Including Both Edge Devices and Alveo Cards","year":"2023"},{"key":"ref9","article-title":"Hls4ml: An open-source codesign workflow to empower scientific low-power machine learning devices","author":"Fahim","year":"2021","journal-title":"arXiv:2103. 05579"},{"key":"ref10","article-title":"A hardware-software blueprint for flexible deep learning specialization","author":"Moreau","year":"2018","journal-title":"arXiv:1807.04188"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2022.3202091"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/CCWC54503.2022.9720794"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ETFA46521.2020.9212130"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM51124.2021.00010"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3242897"},{"key":"ref17","volume-title":"DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)","year":"2023"},{"key":"ref18","first-page":"13","article-title":"Benchmarking quantized neural networks on FPGAs with FINN","volume-title":"Proc. DATE Friday Workshop Syst.-Level Design Methods Deep Learn. Heterogeneous Archit. (SLOHA)","author":"Ducasse"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-78890-6_3"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.3022318"},{"key":"ref21","volume-title":"Brevitas: Quantization-Aware Training in PyTorch","year":"2023"},{"key":"ref22","article-title":"MLPerf tiny benchmark","author":"Banbury","year":"2021","journal-title":"arXiv:2106.07597"},{"key":"ref23","volume-title":"CIFAR-10","author":"Krizhevsky","year":"2023"},{"key":"ref24","volume-title":"Torch2Trt: An Easy to Use PyTorch to TensorRT Converter","year":"2023"},{"key":"ref25","volume-title":"MLPerf Tiny Benchmark Suite","year":"2023"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2016.7929192"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304049"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.12"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439293"},{"key":"ref30","volume-title":"Xilinx VERSAL","year":"2022"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/10005208\/10017269.pdf?arnumber=10017269","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,13]],"date-time":"2024-02-13T07:18:14Z","timestamp":1707808694000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10017269\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023]]},"references-count":30,"URL":"https:\/\/doi.org\/10.1109\/access.2023.3236974","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023]]}}}