{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,25]],"date-time":"2026-06-25T17:26:42Z","timestamp":1782408402228,"version":"3.54.5"},"reference-count":193,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2023]]},"DOI":"10.1109\/access.2023.3252002","type":"journal-article","created":{"date-parts":[[2023,3,3]],"date-time":"2023-03-03T18:25:35Z","timestamp":1677867935000},"page":"22136-22154","source":"Crossref","is-referenced-by-count":15,"title":["Casper: Accelerating Stencil Computations Using Near-Cache Processing"],"prefix":"10.1109","volume":"11","author":[{"ORCID":"https:\/\/orcid.org\/0009-0007-5443-1841","authenticated-orcid":false,"given":"Alain","family":"Denzler","sequence":"first","affiliation":[{"name":"Department of Information Technology and Electrical Engineering (D-ITET), ETH Zürich, Zürich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1557-4819","authenticated-orcid":false,"given":"Geraldo F.","family":"Oliveira","sequence":"additional","affiliation":[{"name":"Department of Information Technology and Electrical Engineering (D-ITET), ETH Zürich, Zürich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Nastaran","family":"Hajinazar","sequence":"additional","affiliation":[{"name":"Department of Information Technology and Electrical Engineering (D-ITET), ETH Zürich, Zürich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Rahul","family":"Bera","sequence":"additional","affiliation":[{"name":"Department of Information Technology and Electrical Engineering (D-ITET), ETH Zürich, Zürich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3502-7401","authenticated-orcid":false,"given":"Gagandeep","family":"Singh","sequence":"additional","affiliation":[{"name":"Department of Information Technology and Electrical Engineering (D-ITET), ETH Zürich, Zürich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6514-1571","authenticated-orcid":false,"given":"Juan","family":"G\u00f3mez-Luna","sequence":"additional","affiliation":[{"name":"Department of Information Technology and Electrical Engineering (D-ITET), ETH Zürich, Zürich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"Department of Information Technology and Electrical Engineering (D-ITET), ETH Zürich, Zürich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2751205.2751223"},{"key":"ref2","volume-title":"Defining Software Requirements for Scientific Computing","author":"Colella","year":"2004"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.5194\/gmd-11-1665-2018"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1111\/j.1365-2478.1983.tb01060.x"},{"key":"ref5","volume-title":"Computational Fluid Dynamics an Introduction","volume":"206","author":"Anderson"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/0165-2125(88)90012-1"},{"key":"ref7","first-page":"89","article-title":"Optimizing stencil computations for NVIDIA Kepler GPUs","volume-title":"Proc. HiStencils","author":"Maruyama"},{"key":"ref8","first-page":"18","article-title":"Towards GPU-accelerated operational weather forecasting","volume-title":"Proc. GTC","author":"Fuhrer"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2014.70"},{"key":"ref10","volume-title":"COSMO Physics Modules are Accelerated as a Part of HP2C Initiative Using OpenACC","year":"2016"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2018.00085"},{"key":"ref12","article-title":"The nonhydrostatic limited-area model LM (lokal-model) of the DWD. Part I: Scientific documentation","author":"Doms","year":"1999"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.70"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1137\/070693199"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1810085.1810096"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1989493.1989508"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2499370.2462176"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-010-0142-5"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2010.2"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-19861-8_13"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/HiPC.2012.6507504"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-007-0111-y"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1111583.1111589"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2751205.2751240"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/CIT.2010.214"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/3243176.3243192"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2016.2614981"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3200691.3178527"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2013.51"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715088"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00050"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240850"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/FPL50879.2020.00014"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/3357526.3357550"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2910824"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/2842615"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.3390\/mi11060622"},{"key":"ref38","first-page":"1","article-title":"Deriving stencil hardware accelerators from a single higher-order function","volume-title":"Proc. CPA","author":"Wester"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/1498765.1498785"},{"key":"ref40","volume-title":"Intel Xeon Processor E7-4850 V4","year":"2016"},{"key":"ref41","volume-title":"APP Metrics for Intel Microprocessors","year":"2022"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-03869-3_72"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2008.5222004"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2010.5470394"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-27562-4_29"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1177\/1094342019828153"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/3501804"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00040"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124544"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/2872887.2750385"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322237"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1007\/978-981-16-7487-7_7"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2019.2934048"},{"key":"ref54","article-title":"Benchmarking a new paradigm: An experimental analysis of a real processing-in-memory architecture","author":"G\u00f3mez-Luna","year":"2021","journal-title":"arXiv:2105.03814"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3174101"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3110993"},{"key":"ref57","article-title":"Enabling the adoption of processing-in-memory: Challenges, mechanisms, future research directions","author":"Ghose","year":"2018","journal-title":"arXiv:1802.00320"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2019.01.009"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322257"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.21"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378497"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123986"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358308"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00022"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322212"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1145\/2872887.2750386"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1186\/s12864-018-4460-0"},{"key":"ref68","article-title":"Active routing: Compute on the way for near-data processing","author":"Puli","year":"2018"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.54"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1145\/3093336.3037702"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446749"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322266"},{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2016.2577557"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480133"},{"key":"ref75","doi-asserted-by":"publisher","DOI":"10.1145\/3296957.3173177"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD50377.2020.00035"},{"key":"ref77","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00081"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001184"},{"key":"ref79","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2021.3088396"},{"key":"ref80","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317867"},{"key":"ref81","doi-asserted-by":"publisher","DOI":"10.1016\/bs.adcom.2017.04.004"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00031"},{"key":"ref83","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3323476"},{"key":"ref84","doi-asserted-by":"publisher","DOI":"10.1145\/2967938.2967940"},{"key":"ref85","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001159"},{"key":"ref86","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1970.5008902"},{"key":"ref87","doi-asserted-by":"publisher","DOI":"10.1109\/2.375174"},{"key":"ref88","doi-asserted-by":"publisher","DOI":"10.1109\/40.592312"},{"key":"ref89","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2015.2409732"},{"key":"ref90","doi-asserted-by":"publisher","DOI":"10.1145\/279361.279387"},{"key":"ref91","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378608"},{"key":"ref92","doi-asserted-by":"publisher","DOI":"10.1145\/514191.514197"},{"key":"ref93","doi-asserted-by":"publisher","DOI":"10.1109\/54.748803"},{"key":"ref94","doi-asserted-by":"publisher","DOI":"10.1145\/1054943.1054946"},{"key":"ref95","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056040"},{"key":"ref96","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001178"},{"key":"ref97","doi-asserted-by":"publisher","DOI":"10.1145\/2600212.2600213"},{"key":"ref98","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123977"},{"key":"ref99","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196029"},{"key":"ref100","doi-asserted-by":"publisher","DOI":"10.1145\/3299874.3317984"},{"key":"ref101","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-56258-2_3"},{"key":"ref102","doi-asserted-by":"publisher","DOI":"10.1145\/3140659.3080233"},{"key":"ref103","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927081"},{"key":"ref104","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00071"},{"key":"ref105","article-title":"In-DRAM bulk bitwise execution engine","author":"Seshadri","year":"2019","journal-title":"arXiv:1905.09822"},{"key":"ref106","article-title":"Buddy-RAM: Improving the performance and efficiency of bulk bitwise operations using DRAM","author":"Seshadri","year":"2016","journal-title":"arXiv:1611.09988"},{"key":"ref107","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2434872"},{"key":"ref108","doi-asserted-by":"publisher","DOI":"10.1109\/PACT52795.2021.00019"},{"key":"ref109","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2021.3065448"},{"key":"ref110","doi-asserted-by":"publisher","DOI":"10.14778\/3137765.3137776"},{"key":"ref111","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480108"},{"key":"ref112","doi-asserted-by":"publisher","DOI":"10.1145\/3503222.3507702"},{"key":"ref113","doi-asserted-by":"publisher","DOI":"10.1145\/290593.290602"},{"key":"ref114","doi-asserted-by":"publisher","DOI":"10.1145\/291006.291026"},{"key":"ref115","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001139"},{"key":"ref116","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898064"},{"key":"ref117","doi-asserted-by":"publisher","DOI":"10.1145\/3296957.3173171"},{"key":"ref118","doi-asserted-by":"publisher","DOI":"10.1145\/3324989.3325723"},{"key":"ref119","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322229"},{"key":"ref120","doi-asserted-by":"publisher","DOI":"10.1109\/40.918001"},{"key":"ref121","first-page":"141","article-title":"The reconfigurable streaming vector processor (RSVP)","volume-title":"Proc. MICRO","author":"Ciricescu"},{"key":"ref122","doi-asserted-by":"publisher","DOI":"10.1145\/3140659.3080255"},{"key":"ref123","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2003.1183532"},{"key":"ref124","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1261383"},{"key":"ref125","doi-asserted-by":"publisher","DOI":"10.1145\/1080695.1070000"},{"key":"ref126","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174248"},{"key":"ref127","volume-title":"ThunderX2 CPU","year":"2022"},{"key":"ref128","doi-asserted-by":"publisher","DOI":"10.1137\/1.9781611971446"},{"key":"ref129","doi-asserted-by":"publisher","DOI":"10.1145\/3563697"},{"key":"ref130","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00011"},{"key":"ref131","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00078"},{"key":"ref132","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474073"},{"key":"ref133","first-page":"185","article-title":"RowClone: Fast and energy-efficient in-DRAM bulk data copy and initialization","volume-title":"Proc. 46th Annu. IEEE\/ACM Int. Symp. Microarchitecture","author":"Seshadri"},{"key":"ref134","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446095"},{"key":"ref135","article-title":"The processing using memory paradigm: In-DRAM bulk copy, initialization, bitwise AND and OR","author":"Seshadri","year":"2016","journal-title":"arXiv:1610.09603"},{"key":"ref136","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783764"},{"key":"ref137","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2013.6670336"},{"key":"ref138","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844483"},{"key":"ref139","doi-asserted-by":"publisher","DOI":"10.1145\/2872887.2750397"},{"key":"ref140","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.42"},{"key":"ref141","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750397"},{"key":"ref142","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001140"},{"key":"ref143","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830820"},{"key":"ref144","doi-asserted-by":"publisher","DOI":"10.1145\/3087556.3087582"},{"key":"ref145","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.22"},{"key":"ref146","doi-asserted-by":"publisher","DOI":"10.1145\/2686875"},{"key":"ref147","doi-asserted-by":"publisher","DOI":"10.1145\/3126908.3126965"},{"key":"ref148","doi-asserted-by":"publisher","DOI":"10.1145\/2771937.2771945"},{"key":"ref149","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2014.6855225"},{"key":"ref150","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783753"},{"key":"ref151","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2821565"},{"key":"ref152","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS47924.2020.00076"},{"key":"ref153","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358256"},{"key":"ref154","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.3013728"},{"key":"ref155","volume-title":"Hybrid Memory Cube Specification Rev. 2.0","year":"2022"},{"key":"ref156","article-title":"Performance exploration of the hybrid memory cube","author":"Rosenfeld","year":"2014"},{"key":"ref157","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2017.8344611"},{"key":"ref158","article-title":"Mapping the Intel last-level cache","author":"Yarom","year":"2015"},{"key":"ref159","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485943"},{"key":"ref160","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1993.393370"},{"key":"ref161","doi-asserted-by":"publisher","DOI":"10.1109\/MM.1997.612174"},{"key":"ref162","article-title":"Design of the RISC-V instruction set architecture","author":"Waterman","year":"2016"},{"key":"ref163","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref164","article-title":"The gem5 simulator: Version 20.0+","author":"Lowe-Power","year":"2020","journal-title":"arXiv:2007.03152"},{"key":"ref165","volume-title":"NVIDIA TITAN V","year":"2022"},{"key":"ref166","doi-asserted-by":"publisher","DOI":"10.1145\/3085572"},{"key":"ref167","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00058"},{"key":"ref168","doi-asserted-by":"publisher","DOI":"10.1145\/3140659.3080214"},{"key":"ref169","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665689"},{"key":"ref170","doi-asserted-by":"publisher","DOI":"10.1109\/secon.2015.7132972"},{"key":"ref171","volume-title":"The NVIDIA Titan V Preview","year":"2017"},{"key":"ref172","volume-title":"PolyBench: The Polyhedral Benchmark Suite","author":"Pouchet","year":"2022"},{"key":"ref173","doi-asserted-by":"publisher","DOI":"10.1109\/TPAMI.1986.4767851"},{"key":"ref174","doi-asserted-by":"publisher","DOI":"10.1145\/2304576.2304619"},{"key":"ref175","volume-title":"Auto-Tuning Stencil Codes for Cache-Based Multicore Platforms","author":"Datta","year":"2009"},{"key":"ref176","doi-asserted-by":"publisher","DOI":"10.1016\/j.camwa.2011.04.012"},{"key":"ref177","doi-asserted-by":"publisher","DOI":"10.1109\/2.809251"},{"key":"ref178","doi-asserted-by":"publisher","DOI":"10.1007\/s00450-011-0191-z"},{"key":"ref179","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2014.6757501"},{"key":"ref180","doi-asserted-by":"publisher","DOI":"10.1145\/2832911"},{"key":"ref181","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-55224-3_54"},{"key":"ref182","doi-asserted-by":"publisher","DOI":"10.1109\/HPCC\/SmartCity\/DSS.2019.00086"},{"key":"ref183","doi-asserted-by":"publisher","DOI":"10.1109\/Cluster48925.2021.00037"},{"key":"ref184","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2014.21"},{"key":"ref185","doi-asserted-by":"publisher","DOI":"10.1109\/CGO51591.2021.9370315"},{"key":"ref186","doi-asserted-by":"publisher","DOI":"10.1145\/3494534"},{"key":"ref187","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062185"},{"key":"ref188","doi-asserted-by":"publisher","DOI":"10.1145\/3461478"},{"key":"ref189","doi-asserted-by":"publisher","DOI":"10.1145\/3352813"},{"key":"ref190","doi-asserted-by":"publisher","DOI":"10.1145\/3572547"},{"key":"ref191","doi-asserted-by":"publisher","DOI":"10.1145\/3297663.3310305"},{"key":"ref192","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375313"},{"key":"ref193","article-title":"Casper: Accelerating stencil computation using near-cache processing","author":"Denzler","year":"2021","journal-title":"arXiv:2112.14216"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/10005208\/10058509.pdf?arnumber=10058509","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,3]],"date-time":"2024-03-03T00:47:37Z","timestamp":1709426857000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10058509\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023]]},"references-count":193,"URL":"https:\/\/doi.org\/10.1109\/access.2023.3252002","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023]]}}}