{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T16:25:04Z","timestamp":1774628704098,"version":"3.50.1"},"reference-count":84,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100003816","name":"Huawei Technologies Research and Development (U.K.) Ltd","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003816","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2023]]},"DOI":"10.1109\/access.2023.3264265","type":"journal-article","created":{"date-parts":[[2023,4,3]],"date-time":"2023-04-03T17:37:37Z","timestamp":1680543457000},"page":"33768-33791","source":"Crossref","is-referenced-by-count":7,"title":["IXIAM: ISA EXtension for Integrated Accelerator Management"],"prefix":"10.1109","volume":"11","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4998-0092","authenticated-orcid":false,"given":"Biagio","family":"Peccerillo","sequence":"first","affiliation":[{"name":"Department of Information Engineering and Mathematics, University of Siena, Siena, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3737-683X","authenticated-orcid":false,"given":"Elham","family":"Cheshmikhani","sequence":"additional","affiliation":[{"name":"Department of Computer Engineering, Amirkabir University of Technology (Tehran Polytechnic), Tehran, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1660-3984","authenticated-orcid":false,"given":"Mirco","family":"Mannino","sequence":"additional","affiliation":[{"name":"Department of Information Engineering and Mathematics, University of Siena, Siena, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andrea","family":"Mondelli","sequence":"additional","affiliation":[{"name":"Huawei Technologies Research and Development (U.K.) Ltd, Cambridge, U.K"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7975-3632","authenticated-orcid":false,"given":"Sandro","family":"Bartolini","sequence":"additional","affiliation":[{"name":"Department of Information Engineering and Mathematics, University of Siena, Siena, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.2877839"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228512"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3282307"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3361682"},{"key":"ref5","doi-asserted-by":"crossref","DOI":"10.1016\/j.sysarc.2022.102561","article-title":"A survey on hardware accelerators: Taxonomy, trends, challenges, and perspectives","volume":"129","author":"Peccerillo","year":"2022","journal-title":"J. Syst. Archit."},{"key":"ref6","volume-title":"AMBA Overview","year":"2023"},{"key":"ref7","volume-title":"M1","year":"2020"},{"key":"ref8","volume-title":"Qualcomm Hexagon DSP: An Architecture Optimized for Mobile and Multimedia Communications","author":"Codrescu","year":"2013"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00053"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080256"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744794"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3126560"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.19"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897972"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2020.i4.239-280"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS45731.2020.9180579"},{"key":"ref17","article-title":"Tightly coupling the PicoRV32 RISC-V processor with custom logic accelerators via a generic interface","author":"Todd","year":"2021"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00015"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080255"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2776954"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3222346"},{"key":"ref22","article-title":"The gem5 simulator: Version 20.0+","author":"Lowe-Power","year":"2020","journal-title":"arXiv:2007.03152"},{"key":"ref23","first-page":"1","article-title":"Toward cache-friendly hardware accelerators","volume-title":"Proc. HPCA Sensors Cloud Archit. Workshop (SCAW)","author":"Shao"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480065"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.3008250"},{"key":"ref26","first-page":"367","article-title":"The forgotten \u2018Uncore\u2019: On the energy-efficiency of heterogeneous cores","volume-title":"Proc. USENIX Annu. Tech. Conf. (USENIX ATC)","author":"Gupta"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.21236\/ada605735"},{"key":"ref28","volume-title":"NVIDIA Ampere GA102 GPU Architecture","year":"2020"},{"key":"ref29","volume-title":"CUDA C Programming Guide","year":"2019"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.2877288"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830821"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ETFA.2017.8247615"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/CCGRID.2007.119"},{"key":"ref34","volume-title":"Understanding the Linux Kernel","author":"Bovet","year":"2005"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/3470496.3527385"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/291006.291020"},{"key":"ref37","volume-title":"Intel 64 and IA-32 Architectures Software Developer\u2019s Manual\u2014Volume 3B","year":"2011"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2491956.2462196"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1995.386540"},{"key":"ref40","volume-title":"A new approach to exclusive data access in shared memory multiprocessors","author":"Jensen","year":"1987"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2500572"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2011.33"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2012.32"},{"key":"ref44","article-title":"Protecting memory-performance critical sections in soft real-time applications","author":"Yun","year":"2015","journal-title":"arXiv:1502.02287"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2013.6531079"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/325096.325100"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541981"},{"key":"ref48","volume-title":"The OpenCL Specification, Version 2.0","author":"Howes","year":"2015"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1145\/2464996.2467280"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/3029580.3029582"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736059"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/HPCS.2018.00117"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2018.2855182"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1145\/1375527.1375566"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1145\/1993498.1993516"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1145\/2259016.2259038"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2018.00091"},{"key":"ref58","volume-title":"NVIDIA TU102","year":"2018"},{"key":"ref59","volume-title":"NVIDIA TU102 Graphics Processing Unit (GPU)","year":"2018"},{"key":"ref60","volume-title":"The Huawei Mate 30 Pro Review: Top Hardware Without Google","year":"2019"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/4.509850"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.6028\/nist.fips.197"},{"key":"ref63","volume-title":"Advanced Encryption Standard (AES) Engine v1.1","year":"2022"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2009.159"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1007\/BFb0028345"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2846688"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.2307\/2003354"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2025803"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref70","volume-title":"Introduction of Uacce","year":"2022"},{"key":"ref71","volume-title":"Welcome to Lord of the IO_Uring","year":"2020"},{"key":"ref72","volume-title":"OpenSSL Cryptography and SSL\/TLS Toolkit","year":"1999"},{"key":"ref73","volume-title":"OpenSSL Cryptography and SSL\/TLS Toolkit GitHub Repository","year":"2022"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2004.840301"},{"key":"ref75","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1145\/3065386"},{"key":"ref77","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref78","article-title":"IntersectX: An efficient accelerator for graph mining","author":"Rao","year":"2020","journal-title":"arXiv:2012.10848"},{"key":"ref79","article-title":"A lightweight ISA extension for AES and SM4","author":"Saarinen","year":"2020","journal-title":"arXiv:2002.07041"},{"key":"ref80","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3063027"},{"key":"ref81","article-title":"Arrow: A RISC-V vector accelerator for machine learning inference","author":"Al Assir","year":"2021","journal-title":"arXiv:2107.07169"},{"key":"ref82","volume-title":"A RISC-V ISA extension for speeding-up post quantum crystals algorithms through HW accelerators integrated in the ariane core pipeline","author":"Albicocchi","year":"2021"},{"key":"ref83","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3093242"},{"key":"ref84","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea12010004"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/10005208\/10091506.pdf?arnumber=10091506","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,29]],"date-time":"2024-02-29T21:03:40Z","timestamp":1709240620000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10091506\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023]]},"references-count":84,"URL":"https:\/\/doi.org\/10.1109\/access.2023.3264265","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023]]}}}