{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,8]],"date-time":"2025-09-08T05:48:22Z","timestamp":1757310502570,"version":"3.40.4"},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"name":"Kaloom, Intel, Noviflow, Prompt Quebec"},{"DOI":"10.13039\/501100000038","name":"Natural Sciences and Engineering Research Council of Canada","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100000038","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2023]]},"DOI":"10.1109\/access.2023.3286726","type":"journal-article","created":{"date-parts":[[2023,6,15]],"date-time":"2023-06-15T17:27:02Z","timestamp":1686850022000},"page":"61422-61436","source":"Crossref","is-referenced-by-count":3,"title":["A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices"],"prefix":"10.1109","volume":"11","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5073-510X","authenticated-orcid":false,"given":"Mostafa","family":"Elbediwy","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, Polytechnique Montr&#x00E9;al, Montreal, QC, Canada"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-5074-3473","authenticated-orcid":false,"given":"Bill","family":"Pontikakis","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Polytechnique Montr&#x00E9;al, Montreal, QC, Canada"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7707-0483","authenticated-orcid":false,"given":"Jean-Pierre","family":"David","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Polytechnique Montr&#x00E9;al, Montreal, QC, Canada"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3404-9959","authenticated-orcid":false,"given":"Yvon","family":"Savaria","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Polytechnique Montr&#x00E9;al, Montreal, QC, Canada"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351332"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3086704"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2834050.2834106"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2018.2886230"},{"key":"ref31","volume":"10","author":"bechtolsheim","year":"2016","journal-title":"Why Big Data Needs Big Buffer Switches"},{"key":"ref30","article-title":"End-to-end window-constrained scheduling for real-time communication","author":"zhang","year":"2004","journal-title":"Proc 10th Int Conf Real-Time Embedded Comput Syst Appl"},{"key":"ref11","first-page":"1","article-title":"Approximating fair queueing on reconfigurable switches","author":"sharma","year":"2018","journal-title":"Proc 15th USENIX Symp Networked Syst Design Implement"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ICCCN.2013.6614175"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000323"},{"journal-title":"Intel Programmable Ethernet Switch Products","year":"2021","key":"ref32"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3341302.3342090"},{"key":"ref1","article-title":"DR-PIFO: A dynamic ranking packet scheduler using push-in-first-out queue","author":"elbediwy","year":"2022","journal-title":"IEEE Trans Netw Service Manag"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICNP52444.2021.9651944"},{"key":"ref16","first-page":"685","article-title":"Programmable calendar queues for high-speed packet scheduling","author":"sharma","year":"2020","journal-title":"Proc 17th USENIX Symp Networked Syst Design Implement"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1016\/j.adhoc.2022.102912"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3452296.3472887"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/REAL.2004.10"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2534169.2486031"},{"journal-title":"802 1Qbb&#x2014;Priority-based Flow Control","year":"2011","author":"desanti","key":"ref26"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2043164.2018443"},{"key":"ref20","first-page":"59","article-title":"SP-PIFO: Approximating push-in first-out behaviors using strict-priority queues","author":"alcoz","year":"2020","journal-title":"Proc 17th USENIX Symp Networked Syst Design Implement"},{"key":"ref22","first-page":"1","article-title":"A probabilistic priority scheduling discipline for high speed networks","author":"jiang","year":"2001","journal-title":"Proc IEEE Workshop High Perform Switching Routing"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/INFOCOMWKSHPS54753.2022.9798055"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2934872.2934900"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/49.772430"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2656877.2656890"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ATC.2016.7764821"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2015.2461602"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1477942.1477944"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3152434.3152457"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2934872.2934899"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"1215","DOI":"10.1109\/12.895938","article-title":"Scalable hardware priority queue architectures for high-speed packet switches","volume":"49","author":"shin","year":"2000","journal-title":"IEEE Trans Comput"},{"key":"ref5","first-page":"51","article-title":"Azure accelerated networking: Smartnics in the public cloud","author":"firestone","year":"2018","journal-title":"Proc 15th USENIX Symp Networked Syst Design Implement"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/10005208\/10153594.pdf?arnumber=10153594","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,16]],"date-time":"2025-04-16T17:52:19Z","timestamp":1744825939000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10153594\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023]]},"references-count":33,"URL":"https:\/\/doi.org\/10.1109\/access.2023.3286726","relation":{},"ISSN":["2169-3536"],"issn-type":[{"type":"electronic","value":"2169-3536"}],"subject":[],"published":{"date-parts":[[2023]]}}}