{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,11]],"date-time":"2026-04-11T22:10:02Z","timestamp":1775945402408,"version":"3.50.1"},"reference-count":16,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"funder":[{"name":"Platform for the Development of Next Generation Integration Circuit Technology"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2023]]},"DOI":"10.1109\/access.2023.3287148","type":"journal-article","created":{"date-parts":[[2023,6,16]],"date-time":"2023-06-16T17:30:39Z","timestamp":1686936639000},"page":"65491-65495","source":"Crossref","is-referenced-by-count":3,"title":["Strained Si Nanosheet pFET Based on SiC Strain Relaxed Buffer Layer for High Performance and Low Power Logic Applications"],"prefix":"10.1109","volume":"11","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4606-7599","authenticated-orcid":false,"given":"Kun","family":"Chen","sequence":"first","affiliation":[{"name":"State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6268-0254","authenticated-orcid":false,"given":"Jingwen","family":"Yang","sequence":"additional","affiliation":[{"name":"State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6630-0757","authenticated-orcid":false,"given":"Chunlei","family":"Wu","sequence":"additional","affiliation":[{"name":"State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9380-8898","authenticated-orcid":false,"given":"Chen","family":"Wang","sequence":"additional","affiliation":[{"name":"State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China"}]},{"given":"Min","family":"Xu","sequence":"additional","affiliation":[{"name":"State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China"}]},{"given":"David Wei","family":"Zhang","sequence":"additional","affiliation":[{"name":"State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1038\/s44172-022-00011-w"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1063\/1.3656989"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1998.746459"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDERC.2017.8066651"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2016.7573416"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/0022-0248(95)00361-4"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIT.2017.7998183"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2017.2695455"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1063\/1.112390"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2014.2364859"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2013.6724615"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2013.6724669"},{"key":"ref4","first-page":"3","article-title":"High performance 14 nm SOI FinFET CMOS technology with 0.0174 ?m2 embedded DRAM and 15 levels of Cu metallization","author":"lin","year":"2014","journal-title":"IEDM Tech Dig"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/SISPAD.2015.7292349"},{"key":"ref6","first-page":"28","article-title":"A novel tensile si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5 nm logic applications and beyond","author":"bae","year":"2016","journal-title":"IEDM Tech Dig"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993490"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/10005208\/10154003.pdf?arnumber=10154003","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,7,24]],"date-time":"2023-07-24T17:57:47Z","timestamp":1690221467000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10154003\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/access.2023.3287148","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023]]}}}