{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,10]],"date-time":"2026-07-10T16:36:28Z","timestamp":1783701388052,"version":"3.55.0"},"reference-count":90,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2023]]},"DOI":"10.1109\/access.2023.3304901","type":"journal-article","created":{"date-parts":[[2023,8,14]],"date-time":"2023-08-14T17:56:40Z","timestamp":1692035800000},"page":"86178-86195","source":"Crossref","is-referenced-by-count":32,"title":["Exploiting the DD-Cell as an Ultra-Compact Entropy Source for an FPGA-Based Re-Configurable PUF-TRNG Architecture"],"prefix":"10.1109","volume":"11","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9990-4875","authenticated-orcid":false,"given":"Riccardo Della","family":"Sala","sequence":"first","affiliation":[{"name":"DIET Department, Sapienza University of Rome, Rome, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5650-8212","authenticated-orcid":false,"given":"Giuseppe","family":"Scotti","sequence":"additional","affiliation":[{"name":"DIET Department, Sapienza University of Rome, Rome, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2019.2926777"},{"key":"ref57","author":"b\u00f6hm","year":"2012","journal-title":"Physical Unclonable Functions in Theory and Practice"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2018.8383890"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2939027"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1117\/12.919920"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2008.4559053"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1002\/jnm.2604"},{"key":"ref58","year":"2010","journal-title":"Towards Hardware-Intrinsic Security"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1587\/transinf.E95.D.426"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-23951-9_2"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/WAINA.2012.12"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/ASICON.2017.8252581"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/RFID.2008.4519377"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2022.3211278"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSTQE.2020.2990216"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1117\/12.2029287"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1298306.1298318"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/AINA.2013.124"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.250627"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3111049"},{"key":"ref90","year":"2010","journal-title":"Spartan-6 FPGA Configurable Logic Block"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-36400-5_30"},{"key":"ref45","first-page":"1672","article-title":"A novel ultra-compact FPGA-compatible TRNG architecture exploiting latched ring oscillators","volume":"69","author":"sala","year":"2022","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref89","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.3000231"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2014.6946136"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577379"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/PRIME55000.2022.9816824"},{"key":"ref86","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.3037173"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.3390\/cryptography5030023"},{"key":"ref85","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.2977920"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2018.i3.267-292"},{"key":"ref88","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-40349-1_11"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2019.2919891"},{"key":"ref87","doi-asserted-by":"publisher","DOI":"10.1049\/cds2.12111"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2019.2926555"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2020.2964435"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/s41635-020-00102-0"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/11605805_8"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2021.3059454"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IVSW.2018.8494884"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-48324-4_28"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/WF-IoT.2016.7845424"},{"key":"ref82","year":"2022","journal-title":"Artix-7 FPGAs Data Sheet DC and AC Switching Characteristics (DS181)"},{"key":"ref81","year":"2019","journal-title":"Vivado Design Suite 7 Series FPGA and ZYNQ-7000 All Programmable SOC Libraries Guide (UG953)"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/JIOT.2022.3224298"},{"key":"ref84","doi-asserted-by":"publisher","DOI":"10.3390\/cryptography5030025"},{"key":"ref83","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3158022"},{"key":"ref80","year":"2016","journal-title":"7 Series FPGAs Configurable Logic Block User Guide (UG474)"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TMSCS.2015.2494014"},{"key":"ref79","doi-asserted-by":"publisher","DOI":"10.1287\/mnsc.21.11.1338"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/3053681"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-15031-9_24"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2020.103180"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2017.7"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2886350"},{"key":"ref75","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2013.6732311"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2018.00090"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.6028\/NIST.SP.800-90B"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/3517813"},{"key":"ref77","doi-asserted-by":"crossref","first-page":"351","DOI":"10.1007\/978-3-642-15031-9_24","article-title":"New high entropy element for FPGA based true random number generators","author":"varchola","year":"2010","journal-title":"Cryptographic Hardware and Embedded Systems, CHES 2010"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.3390\/cryptography7020018"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1109\/4.287"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2320516"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2016.7870046"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/1531542.1531639"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2021.06.001"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1007\/s00145-018-9291-2"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2019.00016"},{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.6028\/NIST.SP.800-22r1a"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2013.2287182"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2636859"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7168788"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2927758"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-16214-0_17"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757433"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870303"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2016.2524666"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.3390\/e24111566"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-74735-2_5"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-12133-3_37"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.3390\/electronics12030755"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-012-0044-0"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2022.105445"},{"key":"ref65","first-page":"2972","article-title":"A lightweight FPGA compatible weak-PUF primitive based on XOR gates","volume":"69","author":"sala","year":"2022","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3206014"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3199218"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2015.2471279"},{"key":"ref60","first-page":"9","article-title":"Physical unclonable functions for device authentication and secret key generation","author":"suh","year":"2007","journal-title":"Proc 44th ACM\/IEEE Design Autom Conf"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-020-00244-5"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2011.6132673"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/10005208\/10216294.pdf?arnumber=10216294","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,4]],"date-time":"2023-09-04T18:13:29Z","timestamp":1693851209000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10216294\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023]]},"references-count":90,"URL":"https:\/\/doi.org\/10.1109\/access.2023.3304901","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023]]}}}