{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,30]],"date-time":"2025-05-30T16:29:24Z","timestamp":1748622564909,"version":"3.37.3"},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100000844","name":"European Space Agency (ESA) with ARQUIMEA Ingenier\u00eda S.L.U","doi-asserted-by":"publisher","award":["4000123942\/18\/NL\/GLC"],"award-info":[{"award-number":["4000123942\/18\/NL\/GLC"]}],"id":[{"id":"10.13039\/501100000844","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Madrid Government (Comunidad de Madrid-Spain) under the Multiannual Agreement with UC3M in the line of Excellence of University Professor","award":["EPUC3M26"],"award-info":[{"award-number":["EPUC3M26"]}]},{"name":"Context of the V Regional Programme of Research and Technological Innovation"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2023]]},"DOI":"10.1109\/access.2023.3325616","type":"journal-article","created":{"date-parts":[[2023,10,18]],"date-time":"2023-10-18T17:55:13Z","timestamp":1697651713000},"page":"116127-116140","source":"Crossref","is-referenced-by-count":2,"title":["Formal Verification of Fault-Tolerant Hardware Designs"],"prefix":"10.1109","volume":"11","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6021-165X","authenticated-orcid":false,"given":"Luis","family":"Entrena","sequence":"first","affiliation":[{"name":"Universidad Carlos III de Madrid, Madrid, Legan\u00e9s, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2142-7885","authenticated-orcid":false,"given":"Antonio J.","family":"S\u00e1nchez-Clemente","sequence":"additional","affiliation":[{"name":"Institute for Applied Microelectronics, Universidad de Las Palmas de Gran Canaria, Campus Universitario de Tarifa, Las Palmas de Gran Canaria, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7287-4477","authenticated-orcid":false,"given":"Luis A.","family":"Garc\u00eda-Astudillo","sequence":"additional","affiliation":[{"name":"Universidad Carlos III de Madrid, Madrid, Legan\u00e9s, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marta","family":"Portela-Garcia","sequence":"additional","affiliation":[{"name":"Universidad Carlos III de Madrid, Madrid, Legan\u00e9s, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1615-1607","authenticated-orcid":false,"given":"Mario","family":"Garcia-Valderas","sequence":"additional","affiliation":[{"name":"Universidad Carlos III de Madrid, Madrid, Legan\u00e9s, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5870-6493","authenticated-orcid":false,"given":"Almudena","family":"Lindoso","sequence":"additional","affiliation":[{"name":"Universidad Carlos III de Madrid, Madrid, Legan\u00e9s, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4843-0507","authenticated-orcid":false,"given":"Roberto","family":"Sarmiento","sequence":"additional","affiliation":[{"name":"Institute for Applied Microelectronics, Universidad de Las Palmas de Gran Canaria, Campus Universitario de Tarifa, Las Palmas de Gran Canaria, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref13","first-page":"502","article-title":"An extensible SAT-solver","volume":"2919","author":"e\u00e9n","year":"2003","journal-title":"Proc SAT"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/12.769433"},{"key":"ref15","first-page":"263","article-title":"Equivalence checking using cuts and heaps","author":"kuehlmann","year":"1997","journal-title":"Proc ACM\/IEEE Des Autom Conf"},{"key":"ref14","first-page":"892","article-title":"A circuit SAT solver with signal correlation guided learning","author":"lu","year":"2003","journal-title":"Proc Eur Design Test Conf"},{"journal-title":"ITC’99 Benchmarks","year":"2019","key":"ref31"},{"key":"ref30","doi-asserted-by":"crossref","first-page":"733","DOI":"10.1109\/TVLSI.2008.2005311","article-title":"SEChecker: A sequential equivalence checking framework based on Kth invariants","volume":"17","author":"lu","year":"2009","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-63104-6_28"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998262"},{"key":"ref2","first-page":"1","article-title":"Verification of triple modular redundancy (TMR) insertion for reliable and trusted systems","author":"berg","year":"2016","journal-title":"Proc MRQW Microelectron Rel Qualification Working Meeting"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1201\/b19714-6"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2002.1012722"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.804386"},{"key":"ref19","first-page":"145","article-title":"Combinational techniques for sequential equivalence checking","author":"savoj","year":"2010","journal-title":"Proc Formal Methods Comput Aided Design"},{"journal-title":"FRAIGs A unifying representation for logic synthesis and verification","year":"2005","author":"mishchenko","key":"ref18"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.811446"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337591"},{"key":"ref26","article-title":"Exhaustively verify SEU mitigation techniques using formal verification","author":"handover","year":"2018","journal-title":"Proc Space FPGA Users Workshop (SEFUW)"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/11560548_20"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2005.1560220"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/12.859539"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2284190"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1976.1674663"},{"key":"ref27","first-page":"27","article-title":"Fault proof: Using formal techniques for safety verification and fault analysis","author":"traskov","year":"2016","journal-title":"Proc Design Verification Conf (DVCon Europe)"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1988.25661"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2791465"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1988.122451"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379017"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/LATW.2018.8349668"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.7717\/peerj-cs.21"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/PACRIM.1997.620351"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/10005208\/10287308.pdf?arnumber=10287308","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,11,13]],"date-time":"2023-11-13T19:39:35Z","timestamp":1699904375000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10287308\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023]]},"references-count":31,"URL":"https:\/\/doi.org\/10.1109\/access.2023.3325616","relation":{},"ISSN":["2169-3536"],"issn-type":[{"type":"electronic","value":"2169-3536"}],"subject":[],"published":{"date-parts":[[2023]]}}}