{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,4]],"date-time":"2026-06-04T16:00:20Z","timestamp":1780588820831,"version":"3.54.1"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2024]]},"DOI":"10.1109\/access.2024.3352266","type":"journal-article","created":{"date-parts":[[2024,1,10]],"date-time":"2024-01-10T20:12:21Z","timestamp":1704917541000},"page":"9418-9439","source":"Crossref","is-referenced-by-count":29,"title":["Design Space Exploration for Edge Machine Learning Featured by MathWorks FPGA DL Processor: A Survey"],"prefix":"10.1109","volume":"12","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8082-2973","authenticated-orcid":false,"given":"Stefano","family":"Bertazzoni","sequence":"first","affiliation":[{"name":"Department of Electronic Engineering, Tor Vergata University of Rome, Rome, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Lorenzo","family":"Canese","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Tor Vergata University of Rome, Rome, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7444-876X","authenticated-orcid":false,"given":"Gian Carlo","family":"Cardarilli","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Tor Vergata University of Rome, Rome, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4312-7939","authenticated-orcid":false,"given":"Luca Di","family":"Nunzio","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Tor Vergata University of Rome, Rome, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7383-2663","authenticated-orcid":false,"given":"Rocco","family":"Fazzolari","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Tor Vergata University of Rome, Rome, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9046-1318","authenticated-orcid":false,"given":"Marco","family":"Re","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Tor Vergata University of Rome, Rome, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8230-7211","authenticated-orcid":false,"given":"Sergio","family":"Span\u00f2","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Tor Vergata University of Rome, Rome, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.3001277"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/j.compeleceng.2022.107749"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVT.2018.2890685"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.energy.2023.128771"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2023.3285279"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DASC\/PiCom\/CBDCom\/Cy55231.2022.9927825"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3204932"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/SiPS52927.2021.00030"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.3390\/electronics10040520"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT47387.2019.00059"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT56656.2022.9974299"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3104644"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/EAIS48028.2020.9122697"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702589"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-93179-7_13"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/s11036-022-01985-9"},{"key":"ref17","volume-title":"Deep Learning HDL Toolbox","year":"2023"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-16281-7_7"},{"key":"ref19","volume-title":"Deep Learning Processor IP Core Architecture","year":"2023"},{"key":"ref20","volume-title":"Supported Networks, Layers, Boards, and Tools","year":"2023"},{"issue":"1","key":"ref21","first-page":"6869","article-title":"Quantized neural networks: Training neural networks with low precision weights and activations","volume":"18","author":"Hubara","year":"2017","journal-title":"J. Mach. Learn. Res."},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/PRIME55000.2022.9816841"},{"key":"ref23","volume-title":"AXI Manager","year":"2023"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2009.5206848"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/10380310\/10387430.pdf?arnumber=10387430","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,3]],"date-time":"2024-03-03T06:34:13Z","timestamp":1709447653000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10387430\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/access.2024.3352266","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024]]}}}