{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,30]],"date-time":"2026-06-30T15:37:40Z","timestamp":1782833860079,"version":"3.54.5"},"reference-count":38,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2024]]},"DOI":"10.1109\/access.2024.3366806","type":"journal-article","created":{"date-parts":[[2024,2,16]],"date-time":"2024-02-16T19:17:40Z","timestamp":1708111060000},"page":"30495-30506","source":"Crossref","is-referenced-by-count":9,"title":["A RISC-V Fault-Tolerant Soft-Processor Based on Full\/Partial Heterogeneous Dual-Core Protection"],"prefix":"10.1109","volume":"12","author":[{"ORCID":"https:\/\/orcid.org\/0009-0003-3882-5147","authenticated-orcid":false,"given":"Francesco","family":"Vigli","sequence":"first","affiliation":[{"name":"Department of Information Engineering, Electronics and Telecommunications (DIET), Sapienza University of Rome, Rome, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1902-7188","authenticated-orcid":false,"given":"Marcello","family":"Barbirotta","sequence":"additional","affiliation":[{"name":"Department of Information Engineering, Electronics and Telecommunications (DIET), Sapienza University of Rome, Rome, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4495-5960","authenticated-orcid":false,"given":"Abdallah","family":"Cheikh","sequence":"additional","affiliation":[{"name":"Department of Information Engineering, Electronics and Telecommunications (DIET), Sapienza University of Rome, Rome, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8453-6536","authenticated-orcid":false,"given":"Francesco","family":"Menichelli","sequence":"additional","affiliation":[{"name":"Department of Information Engineering, Electronics and Telecommunications (DIET), Sapienza University of Rome, Rome, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4243-1258","authenticated-orcid":false,"given":"Antonio","family":"Mastrandrea","sequence":"additional","affiliation":[{"name":"Department of Information Engineering, Electronics and Telecommunications (DIET), Sapienza University of Rome, Rome, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0214-9904","authenticated-orcid":false,"given":"Mauro","family":"Olivieri","sequence":"additional","affiliation":[{"name":"Department of Information Engineering, Electronics and Telecommunications (DIET), Sapienza University of Rome, Rome, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3225975"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TII.2023.3266403"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TMECH.2022.3202642"},{"key":"ref4","first-page":"10","article-title":"Survey of processors for space","volume":"701","author":"Ginosar","year":"2012","journal-title":"DASIA 2012\u2014DAta Systems in Aerospace"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DFT52944.2021.9568368"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1147\/rd.62.0200"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IECON.2019.8926844"},{"key":"ref8","first-page":"1","article-title":"A survey of fault tolerance approaches on different architecture levels","volume-title":"Proc. 30th Int. Conf. Archit. Comput. Syst.","author":"Osinski"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3302255"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2779480"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MCSoC.2016.20"},{"key":"ref12","volume-title":"Benefits of the big.LITTLE architecture","author":"Cho","year":"2012"},{"key":"ref13","doi-asserted-by":"crossref","DOI":"10.1016\/j.mejo.2019.104620","article-title":"Self-healing hardware systems: A review","volume":"93","author":"Khalil","year":"2019","journal-title":"Microelectron. J."},{"key":"ref14","volume-title":"Soft Error Mitigation Controller v4. 1 (PG036)","year":"2015"},{"key":"ref15","volume-title":"Block Memory Generator","year":"2021"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea13010002"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2003.1206992"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.42"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3635161"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.3390\/app8030465"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.5753\/sbesc_estendido.2020.13100"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2015.7477325"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-37277-4_59"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/NGCAS.2017.61"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-93082-4_12"},{"key":"ref26","doi-asserted-by":"crossref","first-page":"529","DOI":"10.1007\/978-3-030-37277-4_62","article-title":"Efficient mathematic accelerator design coupled with an IMT RISC-V microprocessor","volume-title":"Applications in Electronics Pervading Industry, Environment and Society","author":"Cheikh","year":"2020"},{"issue":"17","key":"ref27","doi-asserted-by":"crossref","first-page":"3574","DOI":"10.3390\/electronics12173574","article-title":"Fault-tolerant hardware acceleration for high-performance edge-computing nodes","volume":"12","author":"Barbirotta","year":"2023","journal-title":"Electronics"},{"key":"ref28","first-page":"587","article-title":"An FPGA-based RISC-V computer architecture orbital laboratory on a pocketcube satellite","volume":"173","author":"Blasi","year":"2020","journal-title":"Adv. Astron. Sci."},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2011.06.017"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/DELTA.2008.36"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/OLT.2003.1214387"},{"key":"ref32","article-title":"Predicting on-orbit static single event upset rates in Xilinx Virtex FPGAs","author":"Engel","year":"2006"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/nsrec.2017.8115432"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/REDW.2015.7336736"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/DFT50435.2020.9250871"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2010.5544276"},{"key":"ref37","article-title":"The effect of frequency and technology scaling on single event vulnerability of the combinational logic unit in the LEON2 SPARC V8 processor","volume-title":"Proc. Hardened Electron. Radiat. Technol. Conf.","author":"Duncan"},{"key":"ref38","volume-title":"ECSS-Q-HB-60-02a\u2014Techniques for Radiation Effects Mitigation in Asics and FPGAS Handbook","year":"2016"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/10380310\/10438461.pdf?arnumber=10438461","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,8]],"date-time":"2024-03-08T01:10:01Z","timestamp":1709860201000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10438461\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024]]},"references-count":38,"URL":"https:\/\/doi.org\/10.1109\/access.2024.3366806","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024]]}}}