{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,8]],"date-time":"2026-01-08T07:43:02Z","timestamp":1767858182156,"version":"3.49.0"},"reference-count":21,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"funder":[{"name":"National Key Research and Development Program of China","award":["2022YFB3606900"],"award-info":[{"award-number":["2022YFB3606900"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2024]]},"DOI":"10.1109\/access.2024.3382932","type":"journal-article","created":{"date-parts":[[2024,3,28]],"date-time":"2024-03-28T19:06:24Z","timestamp":1711652784000},"page":"46504-46511","source":"Crossref","is-referenced-by-count":2,"title":["Vertical Surrounding Gate Transistor for High Density and Low Voltage Operation in DRAM"],"prefix":"10.1109","volume":"12","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7555-0328","authenticated-orcid":false,"given":"Wenqi","family":"Wang","sequence":"first","affiliation":[{"name":"Beijing Superstring Academy of Memory Technology, Beijing, China"}]},{"given":"Sang Don","family":"Yi","sequence":"additional","affiliation":[{"name":"Beijing Superstring Academy of Memory Technology, Beijing, China"}]},{"given":"Fu","family":"Li","sequence":"additional","affiliation":[{"name":"Beijing Superstring Academy of Memory Technology, Beijing, China"}]},{"given":"Qingchen","family":"Cao","sequence":"additional","affiliation":[{"name":"Beijing Superstring Academy of Memory Technology, Beijing, China"}]},{"given":"Jiangliu","family":"Shi","sequence":"additional","affiliation":[{"name":"Beijing Superstring Academy of Memory Technology, Beijing, China"}]},{"given":"Bok-Moon","family":"Kang","sequence":"additional","affiliation":[{"name":"Beijing Superstring Academy of Memory Technology, Beijing, China"}]},{"given":"Meichen","family":"Jin","sequence":"additional","affiliation":[{"name":"Beijing Superstring Academy of Memory Technology, Beijing, China"}]},{"given":"Chang","family":"Liu","sequence":"additional","affiliation":[{"name":"Beijing Superstring Academy of Memory Technology, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4552-883X","authenticated-orcid":false,"given":"Zhenhua","family":"Wu","sequence":"additional","affiliation":[{"name":"Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China"}]},{"given":"Guilei","family":"Wang","sequence":"additional","affiliation":[{"name":"Beijing Superstring Academy of Memory Technology, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-2026-2714","authenticated-orcid":false,"given":"Chao","family":"Zhao","sequence":"additional","affiliation":[{"name":"Beijing Superstring Academy of Memory Technology, Beijing, China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/iceca49313.2020.9297568"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ted.2020.2963911"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/icsict55466.2022.9963197"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/iedm19574.2021.9720561"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/essderc.2011.6044197"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1186\/s11671-016-1396-7"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ted.2020.3045966"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/iwaps54037.2021.9671059"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3084447"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-023-01006-x"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.23919\/vlsitechnologyandcir57934.2023.10185353"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1557\/proc-610-b3.2"},{"key":"ref13","first-page":"7.1.1","article-title":"First demonstration of 3D stacked finfets at a 45nm fin pitch and 110nm gate pitch technology on 300 mm wafers","volume-title":"IEDM Tech. Dig.","author":"Vandooren"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/imw56887.2023.10145977"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/iedm.2017.8268472"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1117\/12.2046782"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ted.2016.2601239"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/led.2016.2540645"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ted.2014.2371916"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ted.2012.2185800"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.3390\/electronics9071174"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/10380310\/10483008.pdf?arnumber=10483008","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,4,3]],"date-time":"2024-04-03T17:52:30Z","timestamp":1712166750000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10483008\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/access.2024.3382932","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024]]}}}