{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,21]],"date-time":"2026-03-21T21:14:31Z","timestamp":1774127671722,"version":"3.50.1"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100002322","name":"Coordena\u00e7\u00e3o de Aperfei\u00e7oamento de Pessoal de N\u00edvel Superior","doi-asserted-by":"crossref","award":["001"],"award-info":[{"award-number":["001"]}],"id":[{"id":"10.13039\/501100002322","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100003593","name":"Conselho Nacional de Desenvolvimento Cient\u00edfico e Tecnol\u00f3gico","doi-asserted-by":"crossref","award":["311697\/2022-4"],"award-info":[{"award-number":["311697\/2022-4"]}],"id":[{"id":"10.13039\/501100003593","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Funda\u00e7\u00e3o de Amparo \u00e1 Pesquisa do Estado de Minas Gerais"},{"DOI":"10.13039\/100015772","name":"Pontif\u00edcia Universidade Cat\u00f3lica de Minas Gerais","doi-asserted-by":"crossref","id":[{"id":"10.13039\/100015772","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2024]]},"DOI":"10.1109\/access.2024.3409228","type":"journal-article","created":{"date-parts":[[2024,6,4]],"date-time":"2024-06-04T21:04:40Z","timestamp":1717535080000},"page":"79177-79188","source":"Crossref","is-referenced-by-count":6,"title":["Reinforcement Learning-Based Cache Replacement Policies for Multicore Processors"],"prefix":"10.1109","volume":"12","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9242-9282","authenticated-orcid":false,"given":"Matheus A.","family":"Souza","sequence":"first","affiliation":[{"name":"Department of Computer Science, Pontifícia Universidade Católica de Minas Gerais, Belo Horizonte, Brazil"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9722-1093","authenticated-orcid":false,"given":"Henrique C.","family":"Freitas","sequence":"additional","affiliation":[{"name":"Department of Computer Science, Pontifícia Universidade Católica de Minas Gerais, Belo Horizonte, Brazil"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1147\/sj.52.0078"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.2200\/s00922ed1v01y201905cac047"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-01764-3"},{"key":"ref5","first-page":"3","article-title":"Driving cache replacement with ML-based LeCaR","volume-title":"Proc. 10th USENIX Conf. Hot Topics Storage File Syst.","author":"Vietri"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358319"},{"key":"ref7","first-page":"6237","article-title":"An imitation learning approach for cache replacement","volume-title":"Proc. 37th Int. Conf. Mach. Learn. (ICML)","author":"Liu"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/hpca51647.2021.00033"},{"key":"ref9","volume-title":"Reinforcement Learning: An Introduction","author":"Sutton","year":"2018"},{"key":"ref10","first-page":"1919","article-title":"Learning memory access patterns","volume-title":"Proc. Int. Conf. Mach. Learn.","author":"Hashemi"},{"key":"ref11","first-page":"1","article-title":"Branch prediction as a reinforcement learning problem: Why, how and case studies","volume-title":"Proc. 2nd Workshop Mach. Learn. Comput. Archit. Syst.","author":"Zouzias"},{"key":"ref12","first-page":"1","article-title":"A survey of machine learning applied to computer architecture design","volume-title":"Proc. Int. Workshop AI-Assisted Design Archit.","author":"Penney"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3494523"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/sbac-pad.2012.27"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2629677"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1064978.1065034"},{"key":"ref17","first-page":"469","article-title":"McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures","volume-title":"Proc. 42nd Annu. IEEE\/ACM Int. Symp. Microarchitecture (MICRO)","author":"Li"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/986537.986601"},{"key":"ref19","first-page":"1","article-title":"Cache replacement policy revisited","volume-title":"Proc. Workshop Duplicating, Deconstructing, Debunking","author":"Zahran"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.3892"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/hpca.2017.43"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/isca.2016.17"},{"key":"ref23","first-page":"436","article-title":"Multiperspective reuse prediction","volume-title":"Proc. 50th Annu. IEEE\/ACM Int. Symp. Microarchitecture (MICRO)","author":"Jim\u00e9nez"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1609\/icaps.v32i1.19840"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/6287639\/10380310\/10547236.pdf?arnumber=10547236","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,7,18]],"date-time":"2024-07-18T05:28:21Z","timestamp":1721280501000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10547236\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/access.2024.3409228","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024]]}}}