{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T20:23:12Z","timestamp":1740169392976,"version":"3.37.3"},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"funder":[{"name":"The Alan Turing Institute\u2019s Defence and Security Program"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2024]]},"DOI":"10.1109\/access.2024.3483460","type":"journal-article","created":{"date-parts":[[2024,10,18]],"date-time":"2024-10-18T17:32:26Z","timestamp":1729272746000},"page":"155976-155989","source":"Crossref","is-referenced-by-count":0,"title":["The NAIL Accelerator Interface Layer for Low Latency FPGA Offload"],"prefix":"10.1109","volume":"12","author":[{"given":"Edward","family":"Grindley","sequence":"first","affiliation":[{"name":"The Alan Turing Institute, London, U.K."}]},{"given":"Thurstan","family":"Gray","sequence":"additional","affiliation":[{"name":"The Alan Turing Institute, London, U.K."}]},{"given":"James","family":"Wilkinson","sequence":"additional","affiliation":[{"name":"The Alan Turing Institute, London, U.K."}]},{"given":"Chris","family":"Vaux","sequence":"additional","affiliation":[{"name":"The Alan Turing Institute, London, U.K."}]},{"given":"Adam","family":"Ardron","sequence":"additional","affiliation":[{"name":"The Alan Turing Institute, London, U.K."}]},{"given":"Jack","family":"Deeley","sequence":"additional","affiliation":[{"name":"The Alan Turing Institute, London, U.K."}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-3102-3631","authenticated-orcid":false,"given":"Alexander","family":"Elliott","sequence":"additional","affiliation":[{"name":"The Alan Turing Institute, London, U.K."}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2968-8836","authenticated-orcid":false,"given":"Nidhin","family":"Thandassery Sumithran","sequence":"additional","affiliation":[{"name":"School of Engineering, University of Warwick, Coventry, U.K."}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0568-5048","authenticated-orcid":false,"given":"Suhaib A.","family":"Fahmy","sequence":"additional","affiliation":[{"name":"School of Engineering, University of Warwick, Coventry, U.K."}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2654822.2541967"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3230543.3230560"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3149457.3149479"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2017.37"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-23470-5_1"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927459"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2815631"},{"volume-title":"Xillybus IP Core Product Brief","year":"2022","key":"ref9"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577334"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927507"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00031"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/CloudCom.2015.60"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378491"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439294"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3503222.3507742"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378495"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00014"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICMCCE51767.2020.00109"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2018.00044"},{"key":"ref21","first-page":"250","article-title":"VNFAccel: An FPGA-based platform for modular VNF components acceleration","volume-title":"Proc. IFIP\/IEEE Int. Symp. Integr. Netw. Manage. (IM)","author":"Lopes"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCC.2020.2992548"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3474058"},{"key":"ref24","first-page":"1","article-title":"Agile SoC development with open ESP","volume-title":"Proc. 39th Int. Conf. Comput.-Aided Design","author":"Mantovani"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-021-01640-8"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2012.07.005"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2019.00090"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM48280.2020.00034"},{"volume-title":"UG1399: Vitis High-Level Synthesis User Guide","year":"2021","key":"ref29"},{"volume-title":"Intel High Level Synthesis Compiler Pro Edition: Reference Manual","year":"2021","key":"ref30"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-26408-0_16"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3039902.3039919"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2021.3116859"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2939726"},{"volume-title":"NAIL Repository","year":"2024","key":"ref35"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/6287639\/10380310\/10721468.pdf?arnumber=10721468","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,11,27]],"date-time":"2024-11-27T03:29:11Z","timestamp":1732678151000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10721468\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024]]},"references-count":35,"URL":"https:\/\/doi.org\/10.1109\/access.2024.3483460","relation":{},"ISSN":["2169-3536"],"issn-type":[{"type":"electronic","value":"2169-3536"}],"subject":[],"published":{"date-parts":[[2024]]}}}