{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,4]],"date-time":"2025-06-04T18:10:09Z","timestamp":1749060609272,"version":"3.41.0"},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100003141","name":"Consejo Nacional de Humanidades, Ciencias y Tecnolog\u00edas","doi-asserted-by":"publisher","award":["923824"],"award-info":[{"award-number":["923824"]}],"id":[{"id":"10.13039\/501100003141","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2025]]},"DOI":"10.1109\/access.2025.3531897","type":"journal-article","created":{"date-parts":[[2025,1,20]],"date-time":"2025-01-20T18:59:11Z","timestamp":1737399551000},"page":"93840-93851","source":"Crossref","is-referenced-by-count":0,"title":["Cachedia: An Environment for Efficient Cache Verification With Graphic Visualization for Debugging"],"prefix":"10.1109","volume":"13","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6871-3611","authenticated-orcid":false,"given":"Francisco J.","family":"Rodriguez-Navarrete","sequence":"first","affiliation":[{"name":"Center for Research and Advanced Studies of the National Polytechnic Institute (CINVESTAV), Guadalajara Campus, Zapopan, Mexico"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4802-6632","authenticated-orcid":false,"given":"German","family":"Pinedo-Diaz","sequence":"additional","affiliation":[{"name":"Center for Research and Advanced Studies of the National Polytechnic Institute (CINVESTAV), Guadalajara Campus, Zapopan, Mexico"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L. A.","family":"Luna-Rodriguez","sequence":"additional","affiliation":[{"name":"Universidad Internacional de la Rioja (UNIR), México Campus, Mexico City, Mexico"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6646-1529","authenticated-orcid":false,"given":"Susana","family":"Ortega-Cisneros","sequence":"additional","affiliation":[{"name":"Center for Research and Advanced Studies of the National Polytechnic Institute (CINVESTAV), Guadalajara Campus, Zapopan, Mexico"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7034-8967","authenticated-orcid":false,"given":"L.","family":"Pizano-Escalante","sequence":"additional","affiliation":[{"name":"Systems and IT Department, Electronics, ITESO University, San Pedro Tlaquepaque, Mexico"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8567-4981","authenticated-orcid":false,"given":"J. J.","family":"Raygoza-Panduro","sequence":"additional","affiliation":[{"name":"Department of Electrophotonics, Division of Technologies for Cyber Human Integration, UDG, Guadalajara, Mexico"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","first-page":"1171","article-title":"Design of reconfigurable cache memory using verilog HDL","volume-title":"Proc. Int. Conf. Electr., Electron., Commun., Comput., Optim. Techn. (ICEECCOT)","author":"Manjunatha"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.1999.760030"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/EIConRus.2019.8657064"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.38094\/jastt1329"},{"issue":"8","key":"ref5","first-page":"775","article-title":"Exploring cache coherency design for chip multiprocessor using Multi2Sim","volume":"4","author":"Quang","year":"2015","journal-title":"Int. J. Eng. Res. Technol."},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3510578"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/BEC.2010.5630292"},{"volume-title":"Makerchip\u2014The Most Powerful Verilog Design Environment-for Everyone!","year":"2022","key":"ref8"},{"volume-title":"TL-Verilog","year":"2022","key":"ref9"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICECCME55909.2022.9988191"},{"issue":"2","key":"ref11","doi-asserted-by":"crossref","first-page":"425","DOI":"10.3390\/electronics12020425","article-title":"SHDL\u2014A hardware description language and open-source Web tool for online digital systems design teaching","volume":"12","author":"Trost","year":"2023","journal-title":"Electronics"},{"volume-title":"WebRISC-V: A RISC-V educational simulator featuring RV64IM, pipeline and Web-based UI","year":"2020","author":"Mariotti","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-3558-7_69"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-019-09223-4"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICAIS50930.2021.9396034"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2018.2797253"},{"volume-title":"YOSYS Open Synthesis Suite","year":"2022","author":"Wolf","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3102516"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/IDT.2014.7038594"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2908921"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ECS.2017.8067868"},{"volume-title":"Verilog VCD","year":"2017","author":"As","key":"ref22"},{"key":"ref23","article-title":"Effective design verification\u2014Constrained random with Python and cocotb","author":"Narayan Gadde","year":"2024","journal-title":"arXiv:2407.10312"},{"volume-title":"Prettytable","year":"2023","author":"Abrams","key":"ref24"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.56028\/aetr.4.1.189.2023"},{"volume-title":"PSI HDL Library License, Version 1.0","year":"2022","author":"Purtschert","key":"ref26"},{"volume-title":"Vivado Design Suite TCL Command Reference Guide","year":"2019","key":"ref27"},{"volume-title":"Icarus Verilog","year":"2022","key":"ref28"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/CCE56709.2022.9975965"},{"issue":"8","key":"ref30","doi-asserted-by":"crossref","first-page":"218","DOI":"10.3390\/a14080218","article-title":"IOb-cache: A high-performance configurable open-source cache","volume":"14","author":"Roque","year":"2021","journal-title":"Algorithms"},{"volume-title":"GTKWave: A VCD\/EVCD\/LXT2\/FST Wave Viewer","year":"2024","author":"Bybell","key":"ref31"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/6287639\/10820123\/10847810.pdf?arnumber=10847810","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,4]],"date-time":"2025-06-04T17:57:49Z","timestamp":1749059869000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10847810\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025]]},"references-count":31,"URL":"https:\/\/doi.org\/10.1109\/access.2025.3531897","relation":{},"ISSN":["2169-3536"],"issn-type":[{"type":"electronic","value":"2169-3536"}],"subject":[],"published":{"date-parts":[[2025]]}}}