{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T04:19:41Z","timestamp":1747887581234,"version":"3.41.0"},"reference-count":75,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"name":"European Processor Initiative (EPI) Project from the EuroHPC Joint Undertaking (JU) under Framework Partnership","award":["800928","101036168"],"award-info":[{"award-number":["800928","101036168"]}]},{"name":"European Union\u2019s Horizon 2020 Research and Innovation Program and from Croatia, France, Germany, Greece, Italy, The Netherlands, Portugal, Spain, Sweden, and Switzerland"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2025]]},"DOI":"10.1109\/access.2025.3569533","type":"journal-article","created":{"date-parts":[[2025,5,13]],"date-time":"2025-05-13T17:47:39Z","timestamp":1747158459000},"page":"85898-85926","source":"Crossref","is-referenced-by-count":0,"title":["Memory Prefetching Evaluation of Scientific Applications on a Modern HPC Arm-Based Processor"],"prefix":"10.1109","volume":"13","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6973-4120","authenticated-orcid":false,"given":"Nam","family":"Ho","sequence":"first","affiliation":[{"name":"Jülich Supercomputing Centre, Institute for Advanced Simulation, Forschungszentrum Jülich GmbH, Jülich, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0382-7743","authenticated-orcid":false,"given":"Carlos","family":"Falquez","sequence":"additional","affiliation":[{"name":"Jülich Supercomputing Centre, Institute for Advanced Simulation, Forschungszentrum Jülich GmbH, Jülich, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1319-6404","authenticated-orcid":false,"given":"Antoni","family":"Portero","sequence":"additional","affiliation":[{"name":"Jülich Supercomputing Centre, Institute for Advanced Simulation, Forschungszentrum Jülich GmbH, Jülich, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0748-7264","authenticated-orcid":false,"given":"Estela","family":"Suarez","sequence":"additional","affiliation":[{"name":"Jülich Supercomputing Centre, Institute for Advanced Simulation, Forschungszentrum Jülich GmbH, Jülich, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7296-7817","authenticated-orcid":false,"given":"Dirk","family":"Pleiter","sequence":"additional","affiliation":[{"name":"Division of Computational Science and Technology, EECS, KTH Royal Institute of Technology, Stockholm, Sweden"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/mm.2021.3136882"},{"volume-title":"Alps","year":"2025","key":"ref2"},{"volume-title":"Top500 List","year":"2024","key":"ref3"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/mm.2017.35"},{"volume-title":"Nvidia Grace Hopper Superchip Architecture","year":"2025","key":"ref5"},{"volume-title":"European Processor Initiative","year":"2025","key":"ref6"},{"volume-title":"Arm Neoverse V1 Core-Technical Reference Manual","year":"2021","key":"ref7"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1287\/opre.9.3.383"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/325096.325162"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/C-M.1978.218016"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/12.381947"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1542275.1542349"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830793"},{"key":"ref15","first-page":"247","article-title":"Linearizing irregular memory accesses for improved correlated prefetching","volume-title":"Proc. 46th Annu. IEEE\/ACM Int. Symp. Microarchit. (MICRO)","author":"Jain"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798239"},{"volume-title":"Intel 64 and IA-32 Architectures Optimization Reference Manual","year":"2012","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/hcs59251.2023.10254718"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1190\/1.1441434"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-84882-409-6_8"},{"volume-title":"Minife Finite Element Mini-Applicatio","year":"2024","key":"ref21"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2442516.2442530"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref24","article-title":"The gem5 Simulator: Version 20.0+","author":"Lowe-Power","year":"2020","journal-title":"arXiv:2007.03152"},{"volume-title":"Arm Neoverse V1 Reference Design-software Developer Guide","year":"2021","key":"ref25"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378498"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/bxv112"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ispass.2017.7975288"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2907071"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-01743-8"},{"volume-title":"Arm NeoverseN1 System Development Platform Technical Reference Manual","year":"2020","key":"ref31"},{"volume-title":"Aws Graviton Processor","year":"2022","key":"ref32"},{"volume-title":"POWER8 Processor User\u2019s Manual for Single-Chip Module","year":"2016","key":"ref33"},{"volume-title":"A64FX Microarchitecture Manual","year":"2022","key":"ref34"},{"volume-title":"Intel 64 and IA-32 Architectures Optimization Reference Manual","year":"2024","key":"ref35"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/3274650"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446087"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835971"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.38"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783763"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00021"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10030"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605427"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765944"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830807"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/2925426.2926254"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/3439803"},{"key":"ref48","first-page":"1919","article-title":"Learning memory access patterns","volume-title":"Proc. 35th Int. Conf. Mach. Learn.","author":"Hashemi"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446752"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2749473"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1145\/3345000"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1145\/2133382.2133384"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1145\/3312740"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-10214-6_6"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/hpcs.2018.00061"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1145\/3695794.3695800"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/recosoc.2012.6322869"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2018.00013"},{"volume-title":"AMBA 5 CHI Architecture Specification","year":"2020","key":"ref59"},{"volume-title":"Chi","year":"2021","key":"ref60"},{"volume-title":"Arm Neoverse CMN650 Coherent Mesh Network Technical Reference Manual","year":"2021","key":"ref61"},{"volume-title":"Epi-wp1-public","year":"2021","key":"ref62"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/CLUSTER49012.2020.00079"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2010.144"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-11515-8_10"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1137\/130930352"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/iiswc.2011.6114175"},{"volume-title":"HAICGU Training: Poisson Equation Solving","year":"2023","author":"Pleiter","key":"ref68"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/access.2021.3110993"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2005.59"},{"volume-title":"DAMOV","year":"2022","key":"ref71"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-016-0410-0"},{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1613\/jair.374"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1109\/hpca.2007.346185"},{"key":"ref75","doi-asserted-by":"publisher","DOI":"10.1147\/rd.491.0127"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/6287639\/10820123\/11003053.pdf?arnumber=11003053","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T17:41:04Z","timestamp":1747849264000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11003053\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025]]},"references-count":75,"URL":"https:\/\/doi.org\/10.1109\/access.2025.3569533","relation":{},"ISSN":["2169-3536"],"issn-type":[{"type":"electronic","value":"2169-3536"}],"subject":[],"published":{"date-parts":[[2025]]}}}