{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,18]],"date-time":"2026-04-18T16:43:47Z","timestamp":1776530627221,"version":"3.51.2"},"reference-count":71,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"name":"National Resilience and Recovery Plan (PNRR) through the National Center for HPC, Big Data and Quantum Computing;"},{"name":"ISCRA for the LEONARDO Supercomputer, owned by the EuroHPC Joint Undertaking, hosted by CINECA, Italy"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2025]]},"DOI":"10.1109\/access.2025.3641762","type":"journal-article","created":{"date-parts":[[2025,12,8]],"date-time":"2025-12-08T18:41:50Z","timestamp":1765219310000},"page":"211382-211406","source":"Crossref","is-referenced-by-count":2,"title":["SHADOWFI: An Open-Source Framework for Fault Evaluation of Complex IC Designs Using Hyperscale Computing"],"prefix":"10.1109","volume":"13","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6852-2372","authenticated-orcid":false,"given":"Juan-David","family":"Guerrero-Balaguera","sequence":"first","affiliation":[{"name":"Department of Control and Computer Engineering, Politecnico di Torino (DAUIN), Turin, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5206-3757","authenticated-orcid":false,"given":"Robert","family":"Limas-Sierra","sequence":"additional","affiliation":[{"name":"Department of Control and Computer Engineering, Politecnico di Torino (DAUIN), Turin, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-1319-9462","authenticated-orcid":false,"given":"Oguz","family":"Sensoz","sequence":"additional","affiliation":[{"name":"Department of Control and Computer Engineering, Politecnico di Torino (DAUIN), Turin, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5957-5624","authenticated-orcid":false,"given":"Josie E. Rodriguez","family":"Condia","sequence":"additional","affiliation":[{"name":"Department of Control and Computer Engineering, Politecnico di Torino (DAUIN), Turin, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Maynor Giovanni Ballina","family":"Escobar","sequence":"additional","affiliation":[{"name":"MLab, STI Unit, The Abdus Salam International Centre for Theoretical Physics (ICTP), Trieste, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5483-3388","authenticated-orcid":false,"given":"Maria Liz","family":"Crespo","sequence":"additional","affiliation":[{"name":"MLab, STI Unit, The Abdus Salam International Centre for Theoretical Physics (ICTP), Trieste, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2953-8886","authenticated-orcid":false,"given":"Sergio","family":"Carrato","sequence":"additional","affiliation":[{"name":"Dipartimento di Ingegneria e Architettura (DIA), Universita degli Studi di Trieste (UNITS), Trieste, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2899-7669","authenticated-orcid":false,"given":"Matteo Sonza","family":"Reorda","sequence":"additional","affiliation":[{"name":"Department of Control and Computer Engineering, Politecnico di Torino (DAUIN), Turin, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/mc.2022.3174253"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3676536.3698874"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/EDTM.2019.8731146"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS46558.2021.9405177"},{"issue":"1","key":"ref5","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/TDMR.2021.3131345","article-title":"CMOS reliability from past to future: A survey of requirements, trends, and prediction methods","volume":"22","author":"Hill","year":"2022","journal-title":"IEEE Trans. Device Mater. Rel."},{"key":"ref6","first-page":"1","article-title":"Aging and soft error resilience in reconfigurable CNN accelerators employing a multi-purpose on-chip sensor","volume-title":"Proc. IEEE 25th Latin Amer. Test Symp. (LATS)","author":"Syed"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/LATS58125.2023.10154487"},{"key":"ref8","article-title":"Silent data corruptions at scale","author":"Dixit","year":"2021","journal-title":"arXiv: 2102.11245"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3458336.3465297"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS59296.2023.10224870"},{"key":"ref11","volume-title":"Training in Turmoil: Silent Data Corruption in Systems At Scale","author":"Bonderson","year":"2021"},{"key":"ref12","article-title":"Detection and prevention of silent data corruption in an exabyte-scale database system","volume-title":"Proc. 18th IEEE Workshop Silicon Errors Logic-Syst. Effects","author":"Bacon"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS59296.2023.10224872"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"243","DOI":"10.1007\/978-3-030-18419-3_16","article-title":"When fault injection collides with hardware complexity","volume-title":"Foundations and Practice of Security (FPS 2018)","volume":"11358","author":"Bukasa","year":"2018"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISIEA54517.2022.9873679"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3732777"},{"key":"ref17","first-page":"1","article-title":"A pipelined multi-level fault injector for deep neural networks","volume-title":"Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Nanotechnol. Syst. (DFT)","author":"Ruospo"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ITC50671.2022.00036"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3581784.3607086"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3480962"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"28809","DOI":"10.1109\/ACCESS.2025.3539932","article-title":"RADSAFiE: A netlist-level fault injection user interface application for FPGA-based digital systems","volume":"13","author":"Monopoli","year":"2025","journal-title":"IEEE Access"},{"key":"ref22","article-title":"FLARE: Fault attack leveraging address reconfiguration exploits in multi-tenant FPGAs","author":"Chaudhuri","year":"2025","journal-title":"arXiv:2502.15578"},{"issue":"4","key":"ref23","doi-asserted-by":"crossref","first-page":"807","DOI":"10.3390\/electronics12040807","article-title":"A methodology for accelerating FPGA fault injection campaign using ICAP","volume":"12","author":"Ferlini","year":"2023","journal-title":"Electronics"},{"key":"ref24","first-page":"363","article-title":"CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework","volume-title":"Proc. IEEE Int. Conf. Comput. Design","author":"Pellegrini"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/CloudNet53349.2021.9657109"},{"key":"ref26","volume-title":"Scaled CMOS Technology Reliability Users Guide","year":"2010"},{"key":"ref27","doi-asserted-by":"crossref","first-page":"122","DOI":"10.1016\/j.microrel.2018.04.001","article-title":"Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities","volume":"85","author":"McWilliam","year":"2018","journal-title":"Microelectron. Rel."},{"key":"ref28","volume-title":"Special Functions Units (SFU)","author":"Guerrero-Balaguera","year":"2020"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2004.2"},{"key":"ref30","doi-asserted-by":"crossref","first-page":"169","DOI":"10.1016\/B978-1-78242-221-1.00009-5","article-title":"9-design considerations for reliable embedded systems","volume-title":"Reliability Characterisation of Electrical and Electronic Systems","author":"Shafik","year":"2015"},{"key":"ref31","doi-asserted-by":"crossref","first-page":"617","DOI":"10.1016\/B978-0-12-803738-6.00022-7","article-title":"Chapter 22-advances in GPU reliability research","volume-title":"Advances in GPU Research and Practice","author":"Wadden","year":"2017"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2022.3166260"},{"key":"ref33","doi-asserted-by":"crossref","first-page":"19","DOI":"10.1016\/B978-0-12-824457-9.00001-7","article-title":"Chapter 2-treatise on hazards and risks","volume-title":"Plant Intelligent Automation and Digital Transformation","author":"Basu","year":"2024"},{"issue":"4","key":"ref34","doi-asserted-by":"crossref","first-page":"2728","DOI":"10.1109\/TNS.2013.2267097","article-title":"An automated SEU fault-injection method and tool for HDL-based designs","volume":"60","author":"Mansour","year":"2013","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref35","first-page":"1119","article-title":"Closing the gap between speed and configurability of multi-bit fault emulation environments for security and safety\u2013critical designs","volume-title":"Proc. 17th Euromicro Conf. Digit. Syst. Design","author":"Nyberg"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1007\/s00502-015-0315-4"},{"key":"ref37","first-page":"1","article-title":"Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs","volume-title":"Proc. 24th Int. Conf. Field Program. Log. Appl. (FPL)","author":"Sanchez"},{"key":"ref38","first-page":"1","article-title":"TURTLE: A low-cost fault injection platform for SRAM-based FPGAs","volume-title":"Proc. Int. Conf. ReConFigurable Comput. FPGAs (ReConFig)","author":"Thurlow"},{"key":"ref39","first-page":"159","article-title":"A fault injection methodology and infrastructure for fast single event upsets emulation on Xilinx SRAM-based FPGAs","volume-title":"Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Nanotechnol. Syst. (DFT)","author":"Di Carlo"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-06340-9_6"},{"key":"ref41","first-page":"152","article-title":"Fast single-FPGA fault injection platform","volume-title":"Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Nanotechnol. Syst. (DFT)","author":"Nazar"},{"key":"ref42","first-page":"24","article-title":"Automated SEU fault emulation using partial FPGA reconfiguration","volume-title":"Proc. 13th IEEE Symp. Design Diag. Electron. Circuits Syst.","author":"Legat"},{"key":"ref43","first-page":"1","article-title":"Automatic saboteur placement for emulation-based multi-bit fault injection","volume-title":"Proc. 6th Int. Workshop Reconfigurable Commun.-Centric Syst.-Chip (ReCoSoC)","author":"Grinschgl"},{"key":"ref44","first-page":"327","article-title":"Built-in fault injection in hardware\u2013The FIDYCO example","volume-title":"Proc. 2nd IEEE Int. Workshop Electron. Design, Test Appl.","author":"Rahbaran"},{"issue":"9","key":"ref45","doi-asserted-by":"crossref","first-page":"1459","DOI":"10.1016\/j.microrel.2011.06.017","article-title":"FIFA: A fault-injection\u2013fault-analysis-based tool for reliability assessment at RTL level","volume":"51","author":"Naviner","year":"2011","journal-title":"Microelectron. Rel."},{"issue":"5","key":"ref46","doi-asserted-by":"crossref","first-page":"522","DOI":"10.7763\/IJET.2012.V4.424","article-title":"Implementation of FPGA based fault injection tool (FITO) for testing fault tolerant designs","volume":"4","author":"Rudrakshi","year":"2012","journal-title":"Int. J. Eng. Technol."},{"issue":"2","key":"ref47","doi-asserted-by":"crossref","first-page":"192","DOI":"10.4236\/cs.2012.32026","article-title":"Transient and permanent fault injection in VHDL description of digital circuits","volume":"3","author":"Lala","year":"2012","journal-title":"Circuits Syst."},{"issue":"10","key":"ref48","article-title":"RASP-FIT: A fast and automatic fault injection tool for code-modification of FPGA designs","volume":"9","author":"Khatri","year":"2018","journal-title":"Int. J. Adv. Comput. Sci. Appl."},{"key":"ref49","first-page":"502","article-title":"Statistical fault injection: Quantified error and confidence","volume-title":"Proc. Design, Autom. Test Eur. Conf. Exhib.","author":"Leveugle"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/mcse.2021.3127288"},{"key":"ref51","volume-title":"HyperFPGA: An Experimental Testbed for Heterogeneous Supercomputing","author":"Samayoa"},{"key":"ref52","volume-title":"HyperFPGA: SoC-FPGA Cluster Architecture for Supercomputing and Scientific Applications","author":"Samayoa","year":"2024"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/AICT59525.2023.10313156"},{"key":"ref54","article-title":"Yosys-a free verilog synthesis suite","volume-title":"Proc. 21st Austrian Workshop Microelectron. (Austrochip)","author":"Wolf"},{"key":"ref55","article-title":"Verilator 4.0: Open simulation goes multithreaded","volume-title":"Proc. Open Source Digit. Design Conf. (ORConf)","author":"Snyder"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/JIOT.2025.3547957"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2024.3467089"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2025.3571607"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2025.3554117"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/SPL.2019.8714446"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2025.3534274"},{"key":"ref62","volume-title":"Tensor Core Unit","author":"Condia","year":"2024"},{"key":"ref63","volume-title":"Stereo Vision Core","author":"Guerrero-Balaguera","year":"2024"},{"key":"ref64","volume-title":"Sfu - Piecewise Polynomial Approximation","author":"Nu\u00f1es","year":"2022"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1002\/9781119819820"},{"issue":"1","key":"ref66","doi-asserted-by":"crossref","first-page":"60","DOI":"10.1109\/TCSVT.2012.2203197","article-title":"Improved census transforms for resource-optimized stereo vision","volume":"23","author":"Fife","year":"2013","journal-title":"IEEE Trans. Circuits Syst. Video Technol."},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/BEC49624.2020.9276748"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.52"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS52668.2021.9417025"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3217091"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2023.3330428"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/6287639\/10820123\/11284814.pdf?arnumber=11284814","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,12,19]],"date-time":"2025-12-19T07:49:36Z","timestamp":1766130576000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11284814\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025]]},"references-count":71,"URL":"https:\/\/doi.org\/10.1109\/access.2025.3641762","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025]]}}}