{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,29]],"date-time":"2026-07-29T14:54:25Z","timestamp":1785336865357,"version":"3.55.0"},"reference-count":80,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2026]]},"DOI":"10.1109\/access.2026.3664102","type":"journal-article","created":{"date-parts":[[2026,2,12]],"date-time":"2026-02-12T21:00:51Z","timestamp":1770930051000},"page":"24923-24941","source":"Crossref","is-referenced-by-count":3,"title":["A Comprehensive Survey of Custom Layout Techniques for 6T, 8T, and 10T SRAM Bitcells Across Planar CMOS and FinFET Technology Nodes"],"prefix":"10.1109","volume":"14","author":[{"given":"Ravi S.","family":"Siddanath","sequence":"first","affiliation":[{"name":"Department of ECE, Indian Institute of Information and Technology, Allahabad, Prayagraj, India"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-4522-8533","authenticated-orcid":false,"given":"Sukhen","family":"Mondal","sequence":"additional","affiliation":[{"name":"Department of ECE, Indian Institute of Information and Technology, Allahabad, Prayagraj, India"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Manish","family":"Goswami","sequence":"additional","affiliation":[{"name":"Department of ECE, Indian Institute of Information and Technology, Allahabad, Prayagraj, India"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2683-2230","authenticated-orcid":false,"given":"Kavindra","family":"Kandpal","sequence":"additional","affiliation":[{"name":"Department of ECE, Indian Institute of Information and Technology, Allahabad, Prayagraj, India"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3199077"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3232648"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2024.102225"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1142\/s0218126625503906"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICSC64553.2025.10968087"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2023.3266651"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2019.2900921"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2609386"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2883525"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1088\/1674-4926\/43\/3\/031401"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.3390\/mi15081056"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.3390\/electronics14132719"},{"key":"ref13","doi-asserted-by":"crossref","DOI":"10.21203\/rs.3.rs-3758835\/v1","article-title":"An 8t and 10t static random access memory with bit-serial operations for in-memory computing","author":"Xu","year":"2023"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/s00034-022-02284-0"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3138057"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-0818-5"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2055169"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2022.3165738"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/aeeicb.2016.7538307"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3230046"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/CICC53496.2022.9772789"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ELNANO.2019.8783371"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1016\/j.aeue.2022.154417"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2642198"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/EDSSC.2017.8126401"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705344"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.2197\/ipsjtsldm.4.80"},{"key":"ref28","article-title":"Local bit-line sharing robust dual-port 8T SRAM with virtual VSS for energy-efficient in-memory computing architecture","author":"Rajput","year":"2023","journal-title":"Authorea Preprint"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.917509"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-018-1309-z"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/978-981-99-0973-5_35"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.3390\/electronics10172181"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2023.105795"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/OTCON56053.2023.10113962"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ICDCSyst.2016.7570609"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3079425"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/3182169"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2025.3574413"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320916"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2040094"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.909809"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.3390\/mi15020218"},{"key":"ref43","article-title":"From FinFET to Nanosheet Si-SiGe GAAFET: Fabrication process simulation and analysis","author":"Pelosi","year":"2021"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/ICAIT61638.2024.10690790"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2020.104942"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2024.3355447"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2024.106122"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2023.105729"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1080\/00207217.2023.2238326"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1007\/s00034-024-02718-x"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1145\/3676536.3676784"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586188"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI65124.2025.11130244"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654105"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1145\/3218603.3218645"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/IIRW.2016.7904894"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2022.105449"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/ICCCNT56998.2023.10307771"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/SPECon61254.2024.10537347"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/ECS.2015.7124870"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/CyberC.2015.32"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/UPCON47278.2019.8980049"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1587\/elex.11.20140229"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859025"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-19568-6_5"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1109\/IDT.2008.4802503"},{"key":"ref67","volume-title":"Crosstalk-shielded-bit-line dram","author":"Fifield","year":"1991"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2864267"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2012.6176990"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702518"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705286"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45716-X_6"},{"key":"ref73","volume-title":"Memory formation with reduced metallization layers","author":"Liaw","year":"2009"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1109\/ASQED.2013.6643597"},{"key":"ref75","volume-title":"Memory cell architecture for reduced routing congestion","author":"Ramesh","year":"2005"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2013.6523624"},{"key":"ref77","article-title":"Modeling and simulation of electromigration behavior for via array structure","author":"Airani","year":"2018","journal-title":"arXiv:1801.08281"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1145\/1123008.1123017"},{"key":"ref79","doi-asserted-by":"publisher","DOI":"10.3390\/electronics14153151"},{"key":"ref80","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2003.1183143"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/6287639\/11323511\/11394750.pdf?arnumber=11394750","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,23]],"date-time":"2026-02-23T20:49:30Z","timestamp":1771879770000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11394750\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026]]},"references-count":80,"URL":"https:\/\/doi.org\/10.1109\/access.2026.3664102","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026]]}}}