{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T01:53:32Z","timestamp":1773194012009,"version":"3.50.1"},"reference-count":82,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"crossref","award":["92373106"],"award-info":[{"award-number":["92373106"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100001809","name":"European Union (EU)-Next Generation EU, through the National Recovery and Resilience Plan of the Republic of Bulgaria","doi-asserted-by":"publisher","award":["BG-RRP-2.004-0005"],"award-info":[{"award-number":["BG-RRP-2.004-0005"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2026]]},"DOI":"10.1109\/access.2026.3669612","type":"journal-article","created":{"date-parts":[[2026,3,2]],"date-time":"2026-03-02T20:56:50Z","timestamp":1772485010000},"page":"34894-34915","source":"Crossref","is-referenced-by-count":0,"title":["A Review of Bandwidth Enhancement Techniques for Die-to-Die Single-Ended Interfaces in Chiplets"],"prefix":"10.1109","volume":"14","author":[{"ORCID":"https:\/\/orcid.org\/0009-0008-9805-0562","authenticated-orcid":false,"given":"Haitao","family":"You","sequence":"first","affiliation":[{"name":"Institute of VLSI, College of Integrated Circuits, Zhejiang University, Hangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yixiang","family":"Chen","sequence":"additional","affiliation":[{"name":"Institute of VLSI, College of Integrated Circuits, Zhejiang University, Hangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0586-9923","authenticated-orcid":false,"given":"Li","family":"Zhang","sequence":"additional","affiliation":[{"name":"Institute of VLSI, College of Integrated Circuits, Zhejiang University, Hangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaofang","family":"Gao","sequence":"additional","affiliation":[{"name":"Kunshan Jiwei Microelectronics Technology Company Ltd., Kunshan, Jiangsu, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xinyu","family":"Wu","sequence":"additional","affiliation":[{"name":"Institute of VLSI, College of Integrated Circuits, Zhejiang University, Hangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tianyi","family":"Zhang","sequence":"additional","affiliation":[{"name":"Institute of VLSI, College of Integrated Circuits, Zhejiang University, Hangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shizeng","family":"Zhang","sequence":"additional","affiliation":[{"name":"Institute of VLSI, College of Integrated Circuits, Zhejiang University, Hangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dimitar","family":"Nikolov","sequence":"additional","affiliation":[{"name":"Technical University of Sofia, Sofia, Bulgaria"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-0604-4921","authenticated-orcid":false,"given":"Qiang","family":"Cui","sequence":"additional","affiliation":[{"name":"Institute of VLSI, College of Integrated Circuits, Zhejiang University, Hangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5815-5078","authenticated-orcid":false,"given":"Juin J.","family":"Liou","sequence":"additional","affiliation":[{"name":"College of Electrical and Information Engineering, North Minzu University, Yinchuan, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-DAT52063.2021.9427309"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICEIC57457.2023.10049867"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.future.2017.12.066"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-021-04362-w"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.1998.658762"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050511"},{"issue":"4","key":"ref7","first-page":"154","article-title":"Advanced packaging chiplet technology","volume":"45","author":"Wu","year":"2024","journal-title":"Software"},{"issue":"2","key":"ref8","first-page":"10","article-title":"Development and challenges of Chiplet technology","volume":"24","author":"Chaoyang","year":"2024","journal-title":"Integr. Circuits Embedded Syst."},{"issue":"4","key":"ref9","doi-asserted-by":"crossref","first-page":"670","DOI":"10.3390\/electronics9040670","article-title":"Chiplet heterogeneous integration technology\u2014Status and challenges","volume":"9","author":"Li","year":"2020","journal-title":"Electronics"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/EPTC59621.2023.10457869"},{"issue":"9","key":"ref11","first-page":"51","article-title":"Advances in heterogeneous integrated packaging technology of integrated circuits","volume":"24","author":"Chen","year":"2024","journal-title":"Electron. Packag."},{"issue":"6","key":"ref12","doi-asserted-by":"crossref","first-page":"1455","DOI":"10.1016\/j.fmre.2023.04.014","article-title":"Challenges and prospects for advanced packaging","volume":"4","author":"Chen","year":"2024","journal-title":"Fundam. Res."},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2022.3144461"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/OJSSCS.2024.3506694"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/cicc51472.2021.9431555"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS46773.2023.10181991"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2960207"},{"key":"ref18","volume-title":"Universal Chiplet Interconnect Express (UCIe) Specification","year":"2025"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/A-SSCC67472.2025.11349581"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ESSERC62670.2024.10719524"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3232024"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2024.3436008"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ASICON66040.2025.11326308"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3170439"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MMM.2019.2909517"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365925"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49657.2024.10454320"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42615.2023.10067738"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/A-SSCC56115.2022.9980755"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2023.3269043"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3006864"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49657.2024.10454354"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49657.2024.10454560"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2022.105628"},{"issue":"2","key":"ref35","first-page":"83","article-title":"A low-power and 125 Gb\/s high speed SerDes transmitter using CNRZ-5 for on-chip interconnect","volume":"23","author":"Lv","year":"2022","journal-title":"J. Air Force Eng. Univ. (Natural Sci. Ed.)"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/CICC57935.2023.10121296"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9366048"},{"issue":"2","key":"ref38","first-page":"23","article-title":"Chord signaling techniques for noise cancellation in chiplet interconnect data interfaces","volume":"24","author":"Han","year":"2024","journal-title":"Microcontrollers Embedded Syst. Appl."},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/EDAPS56906.2022.9995425"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/EDAPS50281.2020.9312903"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2962655"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/GEMCCON57842.2023.10078216"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3204744"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3261125"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2015721"},{"key":"ref46","first-page":"145","article-title":"LVDS driver design for high speed serial link in 0.13\u03bc CMOS technology","volume-title":"Proc. Int. Conf. Comput. Problem-Solving (ICCP)","author":"Yang"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3178694"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2016.7841142"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2017.8050879"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/PRIME.2019.8787786"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2008.2006230"},{"issue":"3","key":"ref52","first-page":"338","article-title":"Low-power 10 Gbit\/s transmitter based on SST driver","volume":"48","author":"Liu","year":"2018","journal-title":"Microelectronics"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.3390\/electronics9081315"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063137"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2024.3406928"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3042240"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2359665"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2025.3545483"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2024.3358335"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3104093"},{"issue":"4","key":"ref61","first-page":"68","article-title":"Design of new CTLE equalizer using negative capacitance structure","volume":"29","author":"Lu","year":"2022","journal-title":"Electro-Opt. Control"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.23919\/ICS.2024.3456043"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2873602"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2024.3408648"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/tcsi.2025.3627190"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2466469"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/mwscas.2011.6026319"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1109\/TADVP.2008.924224"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3050823"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1109\/ISNE56211.2023.10221597"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2278804"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1109\/newcas.2015.7182113"},{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.892156"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2022.3208280"},{"key":"ref75","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2258271"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2019.2911017"},{"key":"ref77","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870430"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2746698"},{"issue":"9","key":"ref79","first-page":"2979","article-title":"A 64 Gb\/s single-ended simultaneous bi-directional transceiver for Die-to-Die interfaces","volume":"47","author":"Wang","year":"2025","journal-title":"J. Electron. Inf. Technol."},{"key":"ref80","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2019.2910619"},{"key":"ref81","article-title":"The survey of chiplet-based integrated architecture: An EDA perspective","author":"Chen","year":"2024","journal-title":"arXiv:2411.04410"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC51909.2023.00176"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/6287639\/11323511\/11418640.pdf?arnumber=11418640","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,10]],"date-time":"2026-03-10T05:23:58Z","timestamp":1773120238000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11418640\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026]]},"references-count":82,"URL":"https:\/\/doi.org\/10.1109\/access.2026.3669612","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026]]}}}