{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,10]],"date-time":"2026-04-10T20:53:31Z","timestamp":1775854411088,"version":"3.50.1"},"reference-count":49,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100004787","name":"Estonian Research Council","doi-asserted-by":"publisher","award":["PSG837"],"award-info":[{"award-number":["PSG837"]}],"id":[{"id":"10.13039\/501100004787","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2026]]},"DOI":"10.1109\/access.2026.3680054","type":"journal-article","created":{"date-parts":[[2026,4,2]],"date-time":"2026-04-02T19:51:30Z","timestamp":1775159490000},"page":"52342-52359","source":"Crossref","is-referenced-by-count":0,"title":["RSCAAT: A Recursive Mechanism to Mitigate Cache Side Channel Attacks"],"prefix":"10.1109","volume":"14","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5963-2913","authenticated-orcid":false,"given":"Ameer","family":"Shalabi","sequence":"first","affiliation":[{"name":"Department of Computer Systems, Tallinn University of Technology, Tallinn, Estonia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8021-9368","authenticated-orcid":false,"given":"Tara","family":"Ghasempouri","sequence":"additional","affiliation":[{"name":"Department of Computer Systems, Tallinn University of Technology, Tallinn, Estonia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0745-6743","authenticated-orcid":false,"given":"Peeter","family":"Ellervee","sequence":"additional","affiliation":[{"name":"Department of Computer Systems, Tallinn University of Technology, Tallinn, Estonia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8113-020X","authenticated-orcid":false,"given":"Jaan","family":"Raik","sequence":"additional","affiliation":[{"name":"Department of Computer Systems, Tallinn University of Technology, Tallinn, Estonia"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/633625.52409"},{"key":"ref2","volume-title":"Cache-timing attacks on AES","author":"Bernstein","year":"2005"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2010.5452065"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2007477.1952688"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/11605805_1"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00002"},{"key":"ref7","first-page":"973","article-title":"Meltdown: Reading kernel memory from user space","volume-title":"Proc. 27th USENIX Secur. Symp. (USENIX Security)","author":"Lipp"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/s00145-009-9049-y"},{"key":"ref9","first-page":"719","article-title":"Flush+reload: A high resolution, low noise, L3 cache side-channel attack","volume-title":"Proc. 23rd USENIX Conf. Secur. Symp.","author":"Yarom"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-40667-1_14"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/11935308_9"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1273440.1250723"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/s41635-019-00075-9"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00083"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2086696.2086714"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080222"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.5555\/3241094.3241161"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771781"},{"key":"ref19","first-page":"675","article-title":"Scattercache: Thwarting cache attacks via cache set randomization","volume-title":"Proc. 28th USENIX Secur. Symp.","author":"Werner"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2019.00108"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-008-9018-y"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS52668.2021.9417071"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/DSD51259.2020.00043"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2254064.2254078"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2775054.2694372"},{"key":"ref26","first-page":"341","article-title":"How secure is your cache against side-channel attacks?","volume-title":"Proc. 50th Annu. IEEE\/ACM Int. Symp. Microarchitecture (MICRO)","author":"He"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446082"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/SEED55351.2022.00009"},{"key":"ref29","article-title":"Sasscache: A secure skewed-associative cache with keyed index mapping","volume-title":"Proc. 44th IEEE Symp. Secur. Privacy (SP)","author":"Giner"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2016.85"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00068"},{"key":"ref32","first-page":"1765","article-title":"Mirage: Mitigating conflict-based cache attacks with a practical fully-associative design","volume-title":"Proc. 30th USENIX Secur. Symp. (USENIX Security)","author":"Saileshwar"},{"key":"ref33","first-page":"56","article-title":"PIR-cache: Mitigating conflict-based cache side-channel attacks via partial indirect replacement","volume-title":"Proc. 31st Asia South Pacific Design Autom. Conf. (ASP-DAC)","author":"Song"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/3214292.3214294"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1016\/j.asoc.2016.09.014"},{"key":"ref36","first-page":"564","article-title":"Performance counters to rescue: A machine learning based safeguard against micro-architectural side-channel-attacks","author":"Alam","year":"2017","journal-title":"Cryptol. ePrint Archive"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/FMEC.2018.8364038"},{"key":"ref38","article-title":"Cacheshield: Protecting legacy processes against cache attacks","author":"Briongos","year":"2017","journal-title":"arXiv:1709.01795"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/3214292.3214293"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-45719-2_6"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/ETS48528.2020.9131603"},{"key":"ref42","volume-title":"Chair of VLSI Design, Diagnostics (Don\u2019t Short) and Architecture","year":"2016"},{"key":"ref43","volume-title":"Intel Core i5-4570R Processor (4M Cache, up to 3.20 GHz) \u2014 Product Specifications","year":"2026"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/1241601.1241625"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2016.7482078"},{"key":"ref46","article-title":"Benchmarking modern multiprocessors","author":"Bienia","year":"2008"},{"key":"ref47","first-page":"335","article-title":"Multi2Sim: A simulation framework for CPU-GPU computing","volume-title":"Proc. 21st Int. Conf. Parallel Architectures Compilation Techn. (PACT)","author":"Ubal"},{"key":"ref48","volume-title":"Synopsys Design Compiler: Timing, Area, Power, & Test Optimization","year":"2026"},{"key":"ref49","volume-title":"AMS 0.18 \u03bcm CMOS Process\u2014AMS Process Technology","year":"2026"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/6287639\/11323511\/11471741.pdf?arnumber=11471741","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,4,10]],"date-time":"2026-04-10T20:00:46Z","timestamp":1775851246000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11471741\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026]]},"references-count":49,"URL":"https:\/\/doi.org\/10.1109\/access.2026.3680054","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026]]}}}