{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,20]],"date-time":"2025-11-20T18:28:06Z","timestamp":1763663286458,"version":"3.28.0"},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,11]]},"DOI":"10.1109\/acssc.2014.7094700","type":"proceedings-article","created":{"date-parts":[[2015,4,27]],"date-time":"2015-04-27T16:33:41Z","timestamp":1430152421000},"page":"1440-1444","source":"Crossref","is-referenced-by-count":2,"title":["Automatic generation of application specific FPGA multicore accelerators"],"prefix":"10.1109","author":[{"given":"Andreas Erik","family":"Hindborg","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pascal","family":"Schleuniger","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nicklas Bo","family":"Jense","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Maxwell","family":"Walter","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Laust","family":"Brock-Nannestad","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lars","family":"Bonnichsen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christian W.","family":"Probst","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sven","family":"Karlsson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"article-title":"Performance aspects of syntheizable computing systems","year":"2014","author":"schleuniger","key":"ref10"},{"article-title":"Experiences from developing an optimizing compiler backend for a high performance synthesizable processor","year":"2014","author":"jensen","key":"ref11"},{"article-title":"GHDL-updates repository at SourceForge","year":"2014","author":"gingold","key":"ref12"},{"journal-title":"R Stallman and the GCC Developer Community","article-title":"GNU compiler collection internals, for gcc version 4.9.0","year":"2013","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref15","article-title":"Vivado design suite","volume":"1","author":"feist","year":"2012","journal-title":"Xilinx White Paper Version"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/40.848473"},{"journal-title":"Tensilica","article-title":"XPRES Compiler Product Brief","year":"2005","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.51"},{"key":"ref19","first-page":"518","article-title":"Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip","author":"lyonnard","year":"2001","journal-title":"Design Automation Conference 2001 Proceedings"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853195"},{"journal-title":"Xilinx Inc","article-title":"The Value Of 20nm: Staying A Generation Ahead","year":"2012","key":"ref3"},{"key":"ref6","first-page":"74","article-title":"Synthetic aperture radar data processing on an FPGA multi-core system","author":"schleuniger","year":"2013","journal-title":"Architecture of Computing Systems Springer"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"111","DOI":"10.1007\/978-3-642-28293-5_10","article-title":"Design principles for synthesizable processor cores","volume":"7179","author":"schleuniger","year":"2012","journal-title":"Architecture of Computing Systems ser Lecture Notes in Computer Science Springer"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339272"},{"journal-title":"Fundamentals of Digital Logic With VHDL Design","year":"2000","author":"brown","key":"ref7"},{"journal-title":"Altera Corporation","article-title":"The Breakthrough Advantage for FPGAs with Tri-Gate Technology","year":"2013","key":"ref2"},{"key":"ref1","first-page":"139","article-title":"Accelerator-rich architectures: from single-chip to data-centers","author":"jingsheng","year":"2014","journal-title":"Proceedings of the 2014 International Symposium on Low Power Electronics and ISLPED"},{"journal-title":"Vivado Design Suite User Guide – High-Level Synthesis 2014","article-title":"Xilinx","year":"2014","key":"ref9"},{"key":"ref20","article-title":"Systemcodesigner an automatic esl synthesis approach by design space exploration and behavioral synthesis for streaming applications","volume":"14","author":"lyonnard","year":"2009"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/DASIP.2014.7115604"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MCSoC.2014.30"}],"event":{"name":"2014 48th Asilomar Conference on Signals, Systems and Computers","start":{"date-parts":[[2014,11,2]]},"location":"Pacific Grove, CA, USA","end":{"date-parts":[[2014,11,5]]}},"container-title":["2014 48th Asilomar Conference on Signals, Systems and Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7066991\/7094373\/07094700.pdf?arnumber=7094700","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T06:23:07Z","timestamp":1498198987000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7094700\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,11]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/acssc.2014.7094700","relation":{},"subject":[],"published":{"date-parts":[[2014,11]]}}}