{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,23]],"date-time":"2025-04-23T05:28:41Z","timestamp":1745386121617,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,7]]},"DOI":"10.1109\/actea.2016.7560104","type":"proceedings-article","created":{"date-parts":[[2016,9,5]],"date-time":"2016-09-05T16:21:36Z","timestamp":1473092496000},"page":"16-20","source":"Crossref","is-referenced-by-count":4,"title":["FPGA realization of ALU for mobile GPU"],"prefix":"10.1109","author":[{"given":"Mohammed F.","family":"Tolba","sequence":"first","affiliation":[]},{"given":"Ahmed H.","family":"Madian","sequence":"additional","affiliation":[]},{"given":"Ahmed G.","family":"Radwan","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IDT.2014.7038581"},{"key":"ref11","first-page":"293","article-title":"Multiplication of many-digit numbers by automatic computers","volume":"145","author":"karatsuba","year":"1962","journal-title":"Proceedings of the USSR Academy of Sciences"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ACTEA.2009.5227842"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/NUICONE.2012.6493259"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2043467"},{"key":"ref3","first-page":"177","article-title":"Design and Implementation of A High-speed Reconfigurable Multiplier","author":"wei","year":"2007","journal-title":"Proc IEEE Int ASIC Conf"},{"article-title":"Fast Multiplication: Algorithms And Implementation","year":"1994","author":"bewick","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2009.5117783"},{"key":"ref8","article-title":"Optimized Multiplier based upon 6-Input Luts and Vedic Mathematics","author":"zulhelmi","year":"2013","journal-title":"Proceedings of World Academy of Science Engineering and Technology"},{"key":"ref7","article-title":"High-Speed VLSI Arithmetic Units: Adders and Multipliers in Design of High-Performance Microprocessor Circuits","author":"oklobdzija","year":"2000","journal-title":"IEEE Press"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2423972"},{"article-title":"Computer Arithmetic: Algorithms and Hardware Designs","year":"2010","author":"parahmi","key":"ref1"},{"key":"ref9","article-title":"HDL Implementation of PN Sequence Generator Using Vedic Multiplication and Add &#38; Shift Multiplication","author":"roshni","year":"2015","journal-title":"Communication Systems and Network Technologies (CSNT) 2015 Fifth International Conference on IEEE"}],"event":{"name":"2016 3rd International Conference on Advances in Computational Tools for Engineering Applications (ACTEA)","start":{"date-parts":[[2016,7,13]]},"location":"Zouk Mosbeh, Lebanon","end":{"date-parts":[[2016,7,15]]}},"container-title":["2016 3rd International Conference on Advances in Computational Tools for Engineering Applications (ACTEA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7553649\/7560097\/07560104.pdf?arnumber=7560104","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,9,29]],"date-time":"2016-09-29T12:43:19Z","timestamp":1475152999000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7560104\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,7]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/actea.2016.7560104","relation":{},"subject":[],"published":{"date-parts":[[2016,7]]}}}