{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T10:13:08Z","timestamp":1729678388241,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,6]]},"DOI":"10.1109\/ahs.2010.5546270","type":"proceedings-article","created":{"date-parts":[[2010,8,18]],"date-time":"2010-08-18T14:21:48Z","timestamp":1282141308000},"page":"121-126","source":"Crossref","is-referenced-by-count":3,"title":["A high-throughput, adaptive FFT architecture for FPGA-based space-borne data processors"],"prefix":"10.1109","author":[{"given":"Kayla","family":"Nguyen","sequence":"first","affiliation":[]},{"given":"Jason","family":"Zheng","sequence":"additional","affiliation":[]},{"given":"Yutao","family":"He","sequence":"additional","affiliation":[]},{"given":"Bire","family":"Shah","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CCECE.2005.1557215"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.748190"},{"key":"ref10","article-title":"ISAAC a case of highly-reusable, highly-capable computing and control platform for radar applications","author":"he","year":"2009","journal-title":"Proc of 2009 IEEE Radar Conference"},{"journal-title":"Theory and Application of Digital Signal Processing","year":"1975","author":"rabiner","key":"ref6"},{"key":"ref5","article-title":"Reducing memory references for FFT calculation","author":"aboleaze","year":"2006","journal-title":"Conf Proc of the International Conference on Computer Design"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TAU.1967.1161906"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1090\/S0025-5718-1965-0178586-1"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2002.1010215"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2010.5546279"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"376","DOI":"10.3844\/jcssp.2007.376.382","article-title":"Low power hardware implementation of high speed FFT core","volume":"3","author":"kannan","year":"2007","journal-title":"Journal of Computer Science"}],"event":{"name":"2010 NASA\/ESA Conference on Adaptive Hardware and Systems (AHS)","start":{"date-parts":[[2010,6,15]]},"location":"Anaheim, CA, USA","end":{"date-parts":[[2010,6,18]]}},"container-title":["2010 NASA\/ESA Conference on Adaptive Hardware and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5535249\/5546215\/05546270.pdf?arnumber=5546270","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T08:49:50Z","timestamp":1497862190000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5546270\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,6]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/ahs.2010.5546270","relation":{},"subject":[],"published":{"date-parts":[[2010,6]]}}}