{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T08:28:15Z","timestamp":1725784095245},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,6]]},"DOI":"10.1109\/ahs.2010.5546272","type":"proceedings-article","created":{"date-parts":[[2010,8,18]],"date-time":"2010-08-18T14:21:48Z","timestamp":1282141308000},"page":"113-120","source":"Crossref","is-referenced-by-count":5,"title":["Performance and area efficient transpose memory architecture for high throughput adaptive signal processing systems"],"prefix":"10.1109","author":[{"given":"Mohamed","family":"El-Hadedy","sequence":"first","affiliation":[]},{"given":"Sohan","family":"Purohit","sequence":"additional","affiliation":[]},{"given":"Martin","family":"Margala","sequence":"additional","affiliation":[]},{"given":"Svein J.","family":"Knapskog","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2009.5278014"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-009-0344-5"},{"journal-title":"Multiresolution digital watermarking Algorithms and implications for multimedia signals","year":"1999","author":"kundur","key":"ref10"},{"key":"ref6","article-title":"MORA-An Architecture and Programming Model for a Reconf-name Efficient Coarse Grained Reconfigurable Processor","author":"chalamalasetti","year":"2009","journal-title":"Proc of NASA\/ESA Conference on Adaptive Hardware and Systems"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICOSP.2002.1180098"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/12.859540"},{"journal-title":"Virtex 2 User's Guide","year":"0","key":"ref12"},{"key":"ref8","article-title":"A 167 -processor 65nm Computational Platform with per-Processor Dynamic Supply Voltage","author":"troung","year":"2008","journal-title":"Proceedings of Symposium on VLSI Circuits C 3 1"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310759"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICM.2007.4497658"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1996.564808"},{"key":"ref1","first-page":"232","article-title":"DCT and IDCT Implementations on Different FPGA Technologies","author":"bukhari","year":"2002","journal-title":"Proceedings of ProRISC 2002"}],"event":{"name":"2010 NASA\/ESA Conference on Adaptive Hardware and Systems (AHS)","start":{"date-parts":[[2010,6,15]]},"location":"Anaheim, CA, USA","end":{"date-parts":[[2010,6,18]]}},"container-title":["2010 NASA\/ESA Conference on Adaptive Hardware and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5535249\/5546215\/05546272.pdf?arnumber=5546272","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,19]],"date-time":"2017-03-19T01:13:56Z","timestamp":1489886036000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5546272\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,6]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/ahs.2010.5546272","relation":{},"subject":[],"published":{"date-parts":[[2010,6]]}}}