{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,18]],"date-time":"2026-04-18T16:42:08Z","timestamp":1776530528381,"version":"3.51.2"},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,8]]},"DOI":"10.1109\/ahs.2018.8541485","type":"proceedings-article","created":{"date-parts":[[2018,11,23]],"date-time":"2018-11-23T00:15:58Z","timestamp":1542932158000},"page":"112-119","source":"Crossref","is-referenced-by-count":16,"title":["Approximate TMR for selective error mitigation in FPGAs based on testability analysis"],"prefix":"10.1109","author":[{"given":"Antonio","family":"Sanchez","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luis","family":"Entrena","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fernanda","family":"Kastensmidt","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2008.4484789"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2016.2604918"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2014.6873673"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/LATW.2014.6841916"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2012.6313868"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2014.6873685"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2015.2498313"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"1048","DOI":"10.1109\/43.536711","article-title":"Hope: an efficient parallel fault simulator for synchronous sequential circuits","volume":"15","author":"lee","year":"1996","journal-title":"Computer-Aided Design of Integrated Circuits and Systems IEEE Transactions on"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2016.2541700"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/LATW.2015.7102494"},{"key":"ref4","author":"kastensmidt","year":"2006","journal-title":"Fault-Tolerance Techniques for SRAM-based FPGAs"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2005.860674"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2008.2000852"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/RADECS.2007.5205603"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2006.884352"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2006.251221"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.229"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2004.834955"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2250581"}],"event":{"name":"2018 NASA\/ESA Conference on Adaptive Hardware and Systems (AHS)","location":"Edinburgh","start":{"date-parts":[[2018,8,6]]},"end":{"date-parts":[[2018,8,9]]}},"container-title":["2018 NASA\/ESA Conference on Adaptive Hardware and Systems (AHS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8515683\/8541365\/08541485.pdf?arnumber=8541485","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,27]],"date-time":"2022-01-27T13:51:14Z","timestamp":1643291474000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8541485\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,8]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/ahs.2018.8541485","relation":{},"subject":[],"published":{"date-parts":[[2018,8]]}}}