{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T09:50:21Z","timestamp":1730195421774,"version":"3.28.0"},"reference-count":26,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,8]]},"DOI":"10.1109\/aicas48895.2020.9073877","type":"proceedings-article","created":{"date-parts":[[2020,4,24]],"date-time":"2020-04-24T01:16:57Z","timestamp":1587691017000},"page":"136-140","source":"Crossref","is-referenced-by-count":4,"title":["Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse"],"prefix":"10.1109","author":[{"given":"A.","family":"Laborieux","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Bocquet","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T.","family":"Hirtzlin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.-O.","family":"Klein","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L. Herrera","family":"Diez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Nowak","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Vianello","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.-M.","family":"Portal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"Querlioz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2018.8614642"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2018.10.005"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858419"},{"key":"ref13","article-title":"Adaptive precision cnn accelerator using radix-x parallel connected memristor crossbars","author":"lee","year":"2019","journal-title":"arXiv preprint arXiv 1906 03008"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2017.7966166"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1016\/j.neunet.2018.01.010"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2003.811709"},{"key":"ref17","article-title":"Ternary neural networks with fine-grained quantization","author":"mellempudi","year":"2017","journal-title":"arXiv preprint arXiv 1705 01462"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021740"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2009.2024325"},{"key":"ref4","first-page":"525","article-title":"Xnor-net: Imagenet classification using binary convolutional neural networks","author":"rastegari","year":"2016","journal-title":"Proc ECCV"},{"key":"ref3","article-title":"Binarized neural networks: Training deep neural networks with weights and activations constrained to +1 or ?1","author":"courbariaux","year":"2016","journal-title":"arXiv preprint arXiv 1602 02830"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2018.8614639"},{"key":"ref5","first-page":"345","article-title":"Towards accurate binary convolutional neural network","author":"lin","year":"2017","journal-title":"Advances in neural information processing systems"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2872455"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838429"},{"key":"ref2","first-page":"6869","article-title":"Quantized neural networks: Training neural networks with low precision weights and activations","volume":"18","author":"hubara","year":"2017","journal-title":"The Journal of Machine Learning Research"},{"key":"ref9","first-page":"3","article-title":"Xnor-rram: A scalable and parallel resistive synaptic architecture for binary neural networks","volume":"2","author":"sun","year":"2018","journal-title":"Algorithms"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-018-0059-3"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2034764"},{"key":"ref22","article-title":"Batch normalization: Accelerating deep network training by reducing internal covariate shift","author":"ioffe","year":"2015","journal-title":"arXiv preprint arXiv 1502 03167"},{"key":"ref21","article-title":"Very deep convolutional networks for large-scale image recognition","author":"simonyan","year":"2014","journal-title":"arXiv preprint arXiv 1409 1556"},{"key":"ref24","article-title":"Adam: A method for stochastic optimization","author":"kingma","year":"2014","journal-title":"arXiv preprint arXiv 1412 6980"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2921104"},{"journal-title":"arXiv preprint arXiv 1608 03983","article-title":"Sgdr: Stochastic gradient descent with warm restarts","year":"2016","key":"ref26"},{"key":"ref25","article-title":"Fixing weight decay regularization in adam","author":"loshchilov","year":"2017","journal-title":"arXiv preprint arXiv 1711 05847"}],"event":{"name":"2020 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","start":{"date-parts":[[2020,8,31]]},"location":"Genova, Italy","end":{"date-parts":[[2020,9,2]]}},"container-title":["2020 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9066468\/9072687\/09073877.pdf?arnumber=9073877","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,27]],"date-time":"2022-06-27T15:56:26Z","timestamp":1656345386000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9073877\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,8]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/aicas48895.2020.9073877","relation":{},"subject":[],"published":{"date-parts":[[2020,8]]}}}