{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,29]],"date-time":"2025-08-29T09:50:51Z","timestamp":1756461051731,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,6,13]],"date-time":"2022-06-13T00:00:00Z","timestamp":1655078400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,6,13]],"date-time":"2022-06-13T00:00:00Z","timestamp":1655078400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,6,13]]},"DOI":"10.1109\/aicas54282.2022.9869997","type":"proceedings-article","created":{"date-parts":[[2022,9,5]],"date-time":"2022-09-05T20:21:42Z","timestamp":1662409302000},"page":"469-471","source":"Crossref","is-referenced-by-count":2,"title":["Implementing Binarized Neural Network Processor on FPGA-Based Platform"],"prefix":"10.1109","author":[{"given":"Jeahack","family":"Lee","sequence":"first","affiliation":[{"name":"Korea Electronics Technology Institute,SoC Platform Research Center,Seongnam-si,Korea"}]},{"given":"Hyeonseong","family":"Kim","sequence":"additional","affiliation":[{"name":"Korea Electronics Technology Institute,SoC Platform Research Center,Seongnam-si,Korea"}]},{"given":"Byung-Soo","family":"Kim","sequence":"additional","affiliation":[{"name":"Korea Electronics Technology Institute,SoC Platform Research Center,Seongnam-si,Korea"}]},{"given":"Seokhun","family":"Jeon","sequence":"additional","affiliation":[{"name":"Korea Electronics Technology Institute,SoC Platform Research Center,Seongnam-si,Korea"}]},{"given":"Jung Chul","family":"Lee","sequence":"additional","affiliation":[{"name":"Korea Electronics Technology Institute,SoC Platform Research Center,Seongnam-si,Korea"}]},{"given":"Dong Sun","family":"Kim","sequence":"additional","affiliation":[{"name":"Korea Electronics Technology Institute,SoC Platform Research Center,Seongnam-si,Korea"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-01267-0_44"},{"key":"ref11","article-title":"Back to simplicity: How to train accurate bnns from scratch?","author":"bethge","year":"2019","journal-title":"ArXiv Preprint"},{"key":"ref12","first-page":"16","article-title":"Throughput-optimized OpenCL-based FPGA accelerator for large-scale convolutional neural networks","author":"suda","year":"2016","journal-title":"Proc ACM Int Symp Field-Program Gate Arrays (FPGA)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847265"},{"key":"ref14","first-page":"1","article-title":"A high performance FPGA-based accelerator for large-scale convolutional neural networks","author":"li","year":"2016","journal-title":"Proc IEEE Int Conf on Field Program Logic and Applications (FPL)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021741"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021744"},{"key":"ref4","article-title":"Dorefa-net: Training low bitwidth convolutional neural networks with low bitwidth gradients","author":"zhou","year":"2016","journal-title":"ArXiv Preprint"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.patcog.2020.107281"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-46493-0_32"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/j.neucom.2017.09.046"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00016"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.3390\/electronics8060661"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"436","DOI":"10.1038\/nature14539","article-title":"Deep Learning","volume":"521","author":"lecun","year":"2015","journal-title":"Nature"},{"key":"ref9","article-title":"Fracbnn: Accurate and fpga-efficient binary neural networks with fractional activations","author":"zhang","year":"2020","journal-title":"Int Conf on Learning Representations (ICLR)"}],"event":{"name":"2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS)","start":{"date-parts":[[2022,6,13]]},"location":"Incheon, Korea, Republic of","end":{"date-parts":[[2022,6,15]]}},"container-title":["2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9869844\/9869845\/09869997.pdf?arnumber=9869997","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,9,26]],"date-time":"2022-09-26T21:01:50Z","timestamp":1664226110000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9869997\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6,13]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/aicas54282.2022.9869997","relation":{},"subject":[],"published":{"date-parts":[[2022,6,13]]}}}