{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,3]],"date-time":"2025-12-03T18:10:23Z","timestamp":1764785423692},"reference-count":13,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,4,22]],"date-time":"2024-04-22T00:00:00Z","timestamp":1713744000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,4,22]],"date-time":"2024-04-22T00:00:00Z","timestamp":1713744000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,4,22]]},"DOI":"10.1109\/aicas59952.2024.10595855","type":"proceedings-article","created":{"date-parts":[[2024,7,19]],"date-time":"2024-07-19T17:30:48Z","timestamp":1721410248000},"page":"477-481","source":"Crossref","is-referenced-by-count":1,"title":["Deploying Artificial Intelligence in Design Verification to Accelerate IP\/SoC Sign-off with Zero Escape"],"prefix":"10.1109","author":[{"given":"Surajit","family":"Bhattacherjee","sequence":"first","affiliation":[{"name":"Birla Institute of Technology &#x0026; Science, Pilani, K.K. Birla,Dept. of Electrical &#x0026; Electronics Engg.,Goa,India"}]},{"given":"Daksh","family":"Shah","sequence":"additional","affiliation":[{"name":"Birla Institute of Technology &#x0026; Science, Pilani, K.K. Birla,Dept. of Electrical &#x0026; Electronics Engg.,Goa,India"}]},{"given":"Dipankar","family":"Pal","sequence":"additional","affiliation":[{"name":"Birla Institute of Technology &#x0026; Science, Pilani, K.K. Birla,Dept. of Electrical &#x0026; Electronics Engg.,Goa,India"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/iceccme55909.2022.9987778"},{"volume-title":"NXP: DDR memory module temp sensor with integrated SPD, 3.3 V","key":"ref2"},{"key":"ref3","first-page":"1","article-title":"IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language","year":"2018","journal-title":"IEEE Std 1800-2017 (Revision of IEEE Std 1800-2012)"},{"key":"ref4","first-page":"1","article-title":"IEEE Standard for Universal Verification Methodology Language Reference Manual","year":"2020","journal-title":"IEEE Std 1800.2-2020 (Revision of IEEE Std 1800.2-2017)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/icnc57223.2023.10074542"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/b978-0-12-800727-3.00001-0"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/icais50930.2021.9396034"},{"key":"ref8","first-page":"1","article-title":"IEEE Approved Draft Guide for Architectural Framework and Application of Federated Machine Learning","year":"2020","journal-title":"IEEE P3652.1\/D6.1, July 2020"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CAS52836.2021.9604141"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICIBA50161.2020.9276928"},{"volume-title":"Github: dtreeviz: Decision Tree Visualization","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/niles53778.2021.9600502"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICISSGT52025.2021.00049"}],"event":{"name":"2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS)","start":{"date-parts":[[2024,4,22]]},"location":"Abu Dhabi, United Arab Emirates","end":{"date-parts":[[2024,4,25]]}},"container-title":["2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10595550\/10595552\/10595855.pdf?arnumber=10595855","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,7,20]],"date-time":"2024-07-20T05:02:37Z","timestamp":1721451757000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10595855\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,4,22]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/aicas59952.2024.10595855","relation":{},"subject":[],"published":{"date-parts":[[2024,4,22]]}}}